AD9148BBCZ datasheet(28/73 Pages) AD

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AD9148

Preliminary Technical Data

Rev. PrA | Page 28 of 73

Addr

(Hex)

Bit

Name

Function

Default

PLL Control 2

7:6

DAC CLK to PLL controller clock rate (fPC_CLK).

00 = 2.

01 = 4.

10 = 8.

11 = 16.

fPC_CLK must always be less than 50 MHz.

PLL cross

control enable

Enables PLL cross point control.

3:2

VCO to DACCLK divider.

001

00 = 1.

01 = 2.

10 = 4.

11 = 4.

1:0

DACCLK-to-REFCLK divider.

00 = 2.

01 = 4.

10 = 8.

11 = 16.

PLL Status 0

3:0

PLL control voltage

PLL VCO control voltage readback value.

Read-

only

PLL Status 1

5:0

VCO band readback

VCO band value.

Read-

only

Sync Control 0

Sync enable

Enables synchronization logic.

FIFO rate/data

rate toggle

Operates synchronization at the FIFO reset rate (0)/data rate (1).

Rising edge sync

Rising edge of CLK samples sync input (1), falling edge of

CLK samples sync input (0).

2:0

Sync averaging

Average sync input of number of samples.

000

000 = 1.

001 = 2.

010 = 4.

011 = 8.

100 = 16.

101 = 32.

110 = 64.

111 = 128.

AD9148BBCZ Datasheet(PDF) 28 Page - Analog Devices

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