AD9148BBCZ datasheet(22/73 Pages) AD

22 / 73 page

AD9148

Preliminary Technical Data

Rev. PrA | Page 22 of 73

SPI OPTIONS

The serial port can support both MSB-first and LSB-first data

formats. This functionality is controlled by the LSB first bit

(Register 0x00, Bit 6). The default is MSB first (LSB first = 0).

When LSB first = 0 (MSB first), the instruction and data bit must

be written from MSB to LSB. Multibyte data transfers in MSB-

first format start with an instruction byte that includes the register

address of the most significant data byte. Subsequent data bytes

should follow from the high address to the low address. In MSB-

first mode, the serial port internal byte address generator decrements

for each data byte of the multibyte communication cycle.

When LSB first = 1 (LSB first), the instruction and data bit must

be written from LSB to MSB. Multibyte data transfers in LSB-

first format start with an instruction byte that includes the register

address of the least significant data byte followed by multiple data

bytes. The serial port internal byte address generator increments

for each byte of the multibyte communication cycle.

The serial port controller data address decrements from the data

address written toward 0x00 for multibyte I/O operations if the

MSB-first mode is active. The serial port controller address

increments from the data address written toward 0x1F for

multibyte I/O operations if the LSB-first mode is active.

R/W N1 N0 A4 A3

A2 A1 A0 D7 D6N D5N

D00

D10

D20

D30

D7 D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 41. Serial Register Interface Timing MSB First

A0 A1 A2 A3 A4

N0 N1 R/W D00 D10 D20

D7N

D6N

D5N

D4N

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 42. Serial Register Interface Timing LSB First

INSTRUCTION BIT 6

INSTRUCTION BIT 7

CSB

SCLK

SDIO

tDS

tDCSB

tDH

tPWH

tPWL

tSCLK

Figure 43. Timing Diagram for SPI Register Write

DATA BIT n – 1

DATA BIT n

CSB

SCLK

SDIO

SDO

tDV

Figure 44. Timing Diagram for SPI Register Read

AD9148BBCZ Datasheet(PDF) 22 Page - Analog Devices

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