AD9148BBCZ datasheet(27/73 Pages) AD

27 / 73 page

Preliminary Technical Data

AD9148

Rev. PrA | Page 27 of 73

Addr

(Hex)

Bit

Name

Function

Default

Event Flag 0 (All bits

are high when interrupt

is active. Clear interrupt

by writing respective

bit high.)

PLL lock lost

1 = indicates that the PLL that was previously locked, has

unlocked from the reference signal.

PLL lock

1 = indicates that the PLL has locked to the reference clock

input.

Sync lock lost

1 = indicates that the sync logic that was previously locked,

has lost alignment.

Sync lock

1 = indicates that the sync logic achieved sync alignment. This

is indicated when no phase changes are requested for at least

a few full averaging cycles.

FIFO SPI aligned

1 = indicates that a FIFO reset originating from a serial port-

based request has successfully completed.

FIFO Warning 1

1 = indicates that the difference between the FIFO read and

write pointers is 1.

FIFO Warning 2

1 = indicates that the difference between the FIFO read and

write pointers is 2.

Event Flag 1(All bits are

high when interrupt is

active. Clear interrupt

by writing respective

bit high).

AED compare pass

1 = indicates that the SED logic detected a valid input data

pattern comparison against the preprogrammed expected

values.

AED compare fail

1 = indicates that the SED logic detected an invalid input data

pattern comparison against the preprogrammed expected

values. This automatically clears when eight valid I/Q data

pairs are received.

SED compare fail

1 = indicates that the SED logic detected an invalid input data

pattern comparison against the preprogrammed expected

values.

Clock receiver control

CLK duty

correction

Enables duty-cycle correction on CLK input.

REFCLK duty

correction

Enables duty-cycle correction on REFCLK input.

CLK cross

correction

Enables differential crossing correction on CLK input.

REFCLK cross

correction

Enables differential crossing correction on REFCLK input.

3:0

0111

Always set these bits to 0111

0111

PLL Control 0

PLL enable

Enables PLL clock multiplier.

PLL manual

enable

Enables PLL band selection mode (0 = auto, and 1 = manual).

5:0

Manual VCO band

VCO band used in manual mode.

PLL Control 1

7:5

PLL loop bandwidth

Selects PLL loop filter bandwidth.

110

000 = narrowest bandwidth.

…

111 = widest bandwidth.

4:0

01001

Set these bits to 01001 for optimal PLL operation.

10001

AD9148BBCZ Datasheet(PDF) 27 Page - Analog Devices

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