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AD9148BBCZ Datasheet(PDF) 3 Page - Analog Devices |
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AD9148BBCZ Datasheet(HTML) 3 Page - Analog Devices |
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3 / 73 page  Preliminary Technical Data AD9148 Rev. PrA | Page 3 of 73 FUNCTIONAL BLOCK DIAGRAM 310MHz 310MHz 310MHz/620MHz 500MHz/1GHz 500MHz/1GHz I OFFSET Q OFFSET fS/2 MOD 1.2GHz 1GHz 2× 2× I GAIN Q GAIN 2× 2× 2× 2× I OFFSET COS SIN Q OFFSET GAIN/ OFFSET_CTRL SINC–1 SINC–1 SINC–1 SINC–1 2× 2× I GAIN Q GAIN 2× 2× 2× INTERNAL CLOCK TIMING AND CONTROL LOGIC 2× 16-BIT DAC1 16-BIT DAC2 32-BIT NCO 16-BIT DAC3 16-BIT DAC4 GAIN GAIN AUX1 AUX2 GAIN GAIN AUX3 AUX4 DAC_CLK SYNC REFERENCE BIAS PLL_CTRL CLOCK MULTIPLIER (2× – 16×) MULTI-CHIP SYNC POWER-ON RESET SERIAL IN/OUT PORT PROGRAMMING REGISTERS FRAMEA_P/ FRAMEA_N FRAMEB_P/ FRAMEB_N DCIA_P/ DCIA_N DCIB_P/ DCIB_N B[15:0]_P/ B[15:0]_N A[15:0]_P/ A[15:0]_N 16 16 IOUT1_P IOUT1_N AUX1_P AUX1_N IOUT2_P IOUT2_N AUX2_P AUX2_N IOUT3_P IOUT3_N AUX3_P AUX3_N IOUT4_P IOUT4_N AUX4_P AUX4_N VREF I120 CLK_P CLK_N REFCLK_P/ SYNC_P REFCLK_N/ SYNC_N fS/2 MOD fS/2 MOD fS/2 MOD Figure 2. |
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