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AD9148BBCZ Datasheet(PDF) 71 Page - Analog Devices |
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AD9148BBCZ Datasheet(HTML) 71 Page - Analog Devices |
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71 / 73 page ![]() Preliminary Technical Data AD9148 Rev. PrA | Page 71 of 73 EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9148, certain sequences should be followed. An example start-up routine using the following device configuration is used for this example: • fDATA = 122.88 MSPS • Interpolation = 4×, using HB1 = ’00’ and HB2 = ’000’ • Input data = baseband data • Dual port mode with 1 DCI • fOUT = 140 MHz • fREFCLK = 122.88 MHz • PLL = enabled • Fine NCO = enabled • Inverse SINC Filter = disabled • Synchronization = enabled DERIVED PLL SETTINGS The following PLL settings can be derived from the device configuration: • fDACCLK = fDATA × Interpolation = 491.52 MHz • fVCO = 4 × fDACCLK = 1966.08 MHz (1 GHz < fVCO < 2 GHz) • N1 = fDACCLK/fREFCLK = 4 • N0 = fVCO/fDACCLK = 4 DERIVED NCO SETTINGS The following NCO settings can be derived from the device configuration: • fOUT = 140 MHz • fDACCLK = fDATA × Interpolation = 491.52 MHz • FTW = 140/(491.52) × 232 = 0x48, EAAAAA START-UP SEQUENCE The power clock and register write sequencing for reliable device start-up follows: • Power up the device (no specific power supply sequence is required) • Apply stable REFCLK input signal. • Apply stable DCI input signal. • Issue hardware reset (optional) • Configure device registers with the following write sequence: 0x0C → 0xC9 0x0D → 0xD9 0x0A → 0xC0 0x0A → 0x80 0x10 → 0x48 0x14 → 0x40 0x17 → 0x80 0x17 → 0x00 0x19 → 0x80 0x19 → 0x00 0x1C → 0x40 0x1D → 0x00 0x1E → 0x01 0x54 → 0xAA 0x55 → 0xAA 0x56 → 0xEA 0x57 → 0x48 0x5A → 0x01 0x5A → 0x00 DEVICE VERIFICATION SEQUENCE The following device polling can be conducted to verify the device is working properly: • Read 0x06, Expect Bit 7 = 0, Bit 6 = 1, Bit 5 = 0, Bit 4 = 1, Bit 2 = 1 • Read 0x12, Expect Bit 6 = 1 • Read 0x18, Expect 0x0F (0x07 is also normal) • Read 0x1A, Expect 0x0F (0x07 is also normal) |
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