AD9148BBCZ datasheet(45/73 Pages) AD

45 / 73 page

Preliminary Technical Data

AD9148

Rev. PrA | Page 45 of 73

The following procedure outlines the steps required to

synchronize multiple devices. The procedure assumes that the

REFCLK/SYNC signal is applied to all of the devices and the

PLL of each device is phase locked to it. Each individual device

must follow this procedure.

The procedure for synchronization when using the PLL follows:

Configure for data rate, periodic synchronization by

writing 0xC0 to the sync control register (Register 0x10).

Read the sync status register (Register 0x12) and verify that

the sync locked bit (Bit 6) is set high indicating that the

device achieved back-end synchronization and that the

sync lost bit (Bit 7) is low. These levels indicate that the

clocks are running with a constant and known phase

relative to the sync signal.

Reset the FIFO by strobing the FRAME signal high for at

least the time interval needed to load complete data to the

four DACs. Resetting the FIFO ensures that the correct

data is being read from the FIFO. This completes the

synchronization procedure, and at this stage, all devices

should be synchronized.

To maintain synchronization, the skew between REFCLK/SYNC

signals of the devices must be less than tSKEW nanoseconds. There

is also a setup and hold time to be observed between the DCI and

data of each device and the REFCLK/SYNC signal. When resetting

the FIFO, the FRAME signal must be held high for at least the

time interval needed to load complete data to the four DACs

(one DCI period for dual-port mode and two DCI periods for

single-port or byte mode). A timing diagram of the input signals is

shown in Figure 53.

The example in Figure 53 shows a REFCLK/SYNC frequency equal

to the data rate. While this is the most common situation, it is not

strictly required for proper synchronization. Any REFCLK/SYNC

frequency that satisfies the following equations is acceptable:

fSYNC

= fDACCLK/2N and fSYNC ≤ fDATA

where N = 1, 2, 3, or 4.

For example, a configuration with 4× interpolation and clock

frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, and

fDATA = 200 MHz, fSYNC = 100 MHz would be a viable solution.

REFCLK(1)

REFCLK(2)

DCI(2)

FRAME(2)

tSKEW

tSU_DCI

tH_DCI

Figure 53. Timing Diagram Required for Synchronizing Two Devices

AD9148BBCZ Datasheet(PDF) 45 Page - Analog Devices

AD9148BBCZ Datasheet(HTML) 45 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL