DAC5688 datasheet(39/55 Pages) TI

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400 W

SCLK

SYNC

TXENABLE

DA[15:0]

DB[15:0]

CLKO _CLK 1**

** Asaninput

Internal

digitalin

IOVDD

GND

RESETB

SDENB

Internal

digitalin

IOVDD

GND

400 W

DAC5688

www.ti.com

SLLS880B – DECEMBER 2007 – REVISED MAY 2010

CMOS DIGITAL INPUTS

Figure 43 shows a schematic of the equivalent CMOS digital inputs of the DAC5688. SDIO, SCLK, SYNC,

TXENABLE, DA[15:0] and DB[15:0] have pull-down resistors while RESETB and SDENB have pull-up resistors

internal the DAC5688. See specification table for logic thresholds. The pull-up and pull-down circuitry is

approximately equivalent to 100k

Ω.

The input switches levels for all CMOS digital inputs can be changed from 3.3V input levels to 1.8V input levers

by programming the CONFIG26 io_1p8_3p3 register bit. If io_1p8_3p3 is cleared, the input thresholds are set

for 3.3V CMOS levels. If io_1p8_3p3 is set, the input thresholds are set for 1.8V levels.

Figure 43. CMOS/TTL Digital Equivalent Input

REFERENCE OPERATION

The DAC5688 uses a bandgap reference and control amplifier for biasing the full-scale output current. The

full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through

resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale

output current equals 16 times this bias current and can thus be expressed as:

IOUTFS = 16 × IBIAS = 16 × VEXTIO / RBIAS

Each DAC has a 4-bit independent coarse gain control via coarse_daca(3:0) and coarse_dacb (3:0) in the

CONFIG27 register. Using gain control, the IOUTFS can be expressed as:

IOUTAFS = (DACA_gain + 1) × IBIAS = (DACA_gain + 1) × VEXTIO / RBIAS

IOUTBFS = (DACB_gain + 1) × IBIAS = (DACB_gain + 1) × VEXTIO / RBIAS

where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of

1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor

CEXT of 0.1 mF should be connected externally to terminal EXTIO for compensation. The bandgap reference can

additionally be used for external reference operation. In that case, an external buffer with high impedance input

should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can

be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may hence

be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the

externally applied reference voltage. The internal control amplifier has a wide input range, supporting the

full-scale output current range of 20 dB.

DAC TRANSFER FUNCTION

The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output

current up to 20 mA. Differential current switches direct the current to either one of the complementary output

nodes IOUT1 or IOUT2. (DACA = IOUTA1 or IOUTA2 and DACB = IOUTB1 or IOUTB2.) Complementary output

currents enable differential operation, thus canceling out common mode noise sources (digital feed-through,

on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a

factor of two.

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