DAC5688 datasheet(16/55 Pages) TI

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DAC5688

SLLS880B – DECEMBER 2007 – REVISED MAY 2010

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Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_lock

unused

device_ID (2:0)

version(1:0)

PLL_lock

Asserted when the internal PLL is locked. (Read Only)

device_ID(2:0)

Returns ‘000’ for DAC5688. (Read Only)

version(1:0)

A hardwired register that contains the version of the chip. (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

insel_mode (1:0)

unused

synchr_clkin

twos

inv_inclk

interp_valule(1:0)

insel_mode(1:0)

Controls the expected format of the input data. For the interleaved modes, TXENABLE or the MSB of the port

that does not have data can be used to tell the chip which sample is the A sample. For TXENABLE the sample

aligned with the rising edge is A. For the MSB, it is presumed that this signal will toggle with A and B. The MSB

should be ‘1’ for A and ‘0’ for B. (*** See CONFIG23 ***)

insel_mode

Function

Normal input on A and B.

Interleaved input on A, which is de-interleaved and placed on

both A and B data paths. (*** See CONFIG23 ***)

Interleaved input on B, which is de-interleaved and placed on

both A and B data paths. (*** See CONFIG23 ***)

Half rate data on A and B inputs. This data is merge together

to form a single stream of data on the A data path.

synchr_clkin

This turns on the synchronous mode of the dual-clock in mode. In this mode, the CLK2/C and CLK1/C must be

synchronous in phase since the slower clock is used to synchronize dividers in the clock distribution circuit.

twos

When set (default), the input data format is expected to be 2’s complement. When cleared, the input is

expected to be offset-binary.

inv_inclk

This allows the input clock, the clock driving the input side of the FIFO to be inverted. This allows easier

registering of the data (more setup/hold time) in the single-clock mode of the device

interp_value(1:0)

These bits define the interpolation factor:

interp_value

Interpolation Factor

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