DAC5688 datasheet(24/55 Pages) TI

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DAC5688

SLLS880B – DECEMBER 2007 – REVISED MAY 2010

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Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_LPF_ reset

VCO_div2

PLL_gain(1:0)

PLL_range(3:0)

PLL_LPF_reset

When set, can be used to hold the PLL loop filter at 0 volts.

VCO_div2

When set, the PLL CLOCK output is 1/2 the PLL VCO frequency. Used to run the VCO at 2X the desired clock

frequency to reduce phase noise for lower DAC clock rates.

PLL_gain(1:0)

Used to adjust the PLL’s Voltage Controlled Oscillator (VCO) gain, KVCO. Refer to the Electrical Characteristics

table. By increasing the PLL_gain, the VCO can cover a broader range of frequencies; however, the higher gain

also increases the phase noise of the PLL. In general, lower PLL_gain settings result in lower phase noise. The

KVCO of the VCO can also affect the PLL stability and is used to determine the loop filter components. See section

on determining the PLL filter components for more detail.

PLL_range(3:0)

Used to adjust the bias current of the VCO. By increasing the bias current, the oscillator can reach higher

frequencies. Refer to the Electrical Characteristics table.

'0000' – minimum bias current and lowest VCO frequency range

'1111' – maximum bias current and highest VCO frequency range

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DAC5688 Datasheet(PDF) 24 Page - Texas Instruments