DAC5688 datasheet(18/55 Pages) TI

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DAC5688

SLLS880B – DECEMBER 2007 – REVISED MAY 2010

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Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

sif4

sif_ sync_sig

clkdiv_sync_ena

clkdiv_sync_sel

Reserved

clkdiv_shift

mixer_gain

unused

sif4

When set, the serial interface (SIF) is a 4 bit interface, otherwise it is a 3 bit interface.

sif_sync_sig

SIF created sync signal. Set to ‘1’ to cause a sync and then clear to ‘0’ to remove it.

clkdiv_sync_ena

Enables syncing of the clock divider using the sync or TXENABLE pins when the bit is asserted.

clkdiv_sync_sel

Selects the input pin to sync the clock dividers. (0 = SYNC, 1 = TXENABLE)

clkdiv_shift

When set, a rising edge on the selected sync (see clkdiv_sync_sel) for the clock dividers will cause a slip in the

synchronous counter by 1T and is useful for multi-DAC time alignment.

mixer_gain

When set, adds 6dB to the mixer gain output.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

phaseoffset(7:0)

See CONFIG7 below.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

phaseoffset(15:8)

This is the phase offset added to the NCO accumulator just before generation of the SIN and COS values. The

phase offset is added to the upper 16bits of the NCO accumulator results and these 16 bits are used in the

sin/cosine lookup tables.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

phaseadd(7:0)

See CONFIG11 below.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

phaseadd(15:8)

See CONFIG11 below.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

phaseadd(23:16)

See CONFIG11 below.

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