DAC5688 datasheet(21/55 Pages) TI

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DAC5688

www.ti.com

SLLS880B – DECEMBER 2007 – REVISED MAY 2010

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

qmc_offseta(12:8)

unused

qmc_offseta(12:8)

: Upper 5 bits of the DACA offset correction.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

qmc_offsetb(12:8)

unused

qmc_offsetb(12:8)

: Upper 5 bits of the DACB offset correction.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ser_dac_data(7:0)

Lower 8 bits of the serial interface controlled DAC value. This data is routed to both DACs when enabled

via ser_dac_data_ena in CONFIG4. Value is expected in 2s complement format.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ser_dac_data(15:8)

Upper 8 bits of the serial interface controlled DAC value. This data is routed to both DACs when enabled via

ser_dac_data_ena in CONFIG4. Value is expected in 2's complement format.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

nco_sel(1:0)

nco_reg_sel(1:0)

qmcorr_reg_sel(1:0)

qmoffset_reg_sel(1:0)

nco_sel(1:0)

Selects the signal to use as the sync for the NCO accumulator.

nco_reg_sel(1:0)

Selects the signal to use as the sync for loading the NCO registers.

qmcorr_reg_sel(1:0)

Selects the signal to use as the sync for loading the QM correction registers.

qmoffsest_reg_sel(1:0)

Selects the signal to use as the sync for loading the QM offset correction registers.

*_sel (1:0)

Sync selected

TXENABLE from FIFO output

SYNC from FIFO output

sync_SIF_sig (via CONFIG5)

Always zero

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