DAC5688 datasheet(45/55 Pages) TI

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C1 + t1 1 *

C2 +

t1 * t2

R1 +

t32

t1(t3 * t2)

t1 +

dKvco

tan f

d ) sec

t2 +

d tan

d ) sec

t3 +

tan f

d ) sec

DAC5688

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SLLS880B – DECEMBER 2007 – REVISED MAY 2010

RECOMMENDED STARTUP SEQUENCE

The following startup sequence is recommend to initialization the DAC5688:

1. Supply all 1.8V (CLKVDD, DVDD, VFUSE) and 3.3V (AVDD and IOVDD) voltages.

2. Toggle RESETB pin for a minimum 25 nSec active low pulse width.

3. Provide a stable CLK2/C input clock.

4. Program all desired SIF registers.

5. Provide a sync signal to all digital blocks. The sync input source may be either TXENABLE pin, SYNC pin or

a software sync via CONFIG5 sif_sync_sig bit; however, only the TXENABLE or SYNC pins are

recommended for multi-DAC synchronization. Refer to CONFIG5, CONFIG22 and CONFIG23 registers for

sync source selection. Note: Registers CONFIG6 through CONFIG13 all require a sync input to transfer the

contents of the control register inputs to the active digital blocks.

6. Provide data flow.

MULTI-DAC SYNCHRONIZATION

If the system has two or more DACs requiring synchronization, the sync signal in Step 5 of the RECOMMENDED

STARTUP SEQUENCE must be provided to all the DACs simultaneously. The sync input source must be either

the TXENABLE pin or the SYNC pin (the software sync is not recommended).

In some applications such as beamforming it is required that the multiple DACs in the system have constant

latency thus resulting in phase aligned outputs. As a result of the clock domain transfer on the DAC5688 FIFO,

the outputs of all DACs can only be synchronized to within ±1 DAC clock cycle in the External and Dual Clock

modes. In order to guarantee exact phase alignment between all devices it is required to set up the device in

Dual Synchronous Clock mode.

DESIGNING THE PLL LOOP FILTER

To minimize phase noise given for a given fDAC and M/N, the values of PLL_gain and PLL_range are selected

so that GVCO is minimized and within the MIN and MAX frequency for a given setting.

The external loop filter components C1, C2, and R1 are set by the GVCO, M/N, the loop phase margin fd and the

loop bandwidth wd. Except for applications where abrupt clock frequency changes require a fast PLL lock time, it

is suggested that fd be set to at least 80 degrees for stable locking and suppression of the phase noise side

lobes. Phase margins of 60 degrees or less can be sensitive to board layout and decoupling details.

See Figure 52 for the recommend external loop filter topology. C1, C2, and R1 are calculated by the following

equations

(5)

where

(6)

charge pump current: Iqp = 1 mA

vco gain: KVCO = 2p × GVCO rad/V

PFD Frequency: wd ≤ 160 MHz

phase detector gain: Kd = Iqp ÷ (2 × p × M) A/rad

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