DAC5688 datasheet(22/55 Pages) TI

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DAC5688

SLLS880B – DECEMBER 2007 – REVISED MAY 2010

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Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

unused

fifo_sel(2:0)

aflag_ sel

unused

fifo_sel(2:0)

Selects the sync source for the FIFO from the table below. For the case where the sync is dependent on the first

transition of the input data MSB: Once the transition occurs, the only way to get another sync it to reset the device

or to program fifo_sel to another value

fifo_sel (2:0)

Sync selected

000

TXENABLE from pin

001

SYNC from pin

010

sync_SIF_sig (via CONFIG5)

011

Always zero

100

1st transition on DA MSB

101

1st transition on DB MSB

110

Always zero

111

Always one

aflag_sel

When set, the MSB of the input opposite of incoming data is used to determine the A sample. When cleared,

rising edge of TXENABLE is used. Refer to Figure 37.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

fifo_sync_strt(3:0)

Unused

fifo_sync_strt(3:0)

When the sync to the FIFO occurs, this is the value loaded into the FIFO output position counter. With this

value the initial difference between input and output pointers can be controlled. This may be helpful in

syncing multiple chips or controlling the delay through the device.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

io_1p8_3p3

Unused

sleepb

sleepa

isbiaslpfb_a

isbiaslpf_b

PLL_ sleep

PLL_ena

io_1p8_3p3

Used to program the digital input voltage threshold levels. ‘0’=3.3V tolerate pads and ‘1’=1.8V tolerate pads.

Applies to following digital pins: CLKO_CLK1, LOCK_CLK1C, DA[15:0], DB[15:0], SYNC, RESETB, SCLK,

SDENB, SDIO (input only) and TXENABLE.

sleepb

When set, DACB is put into sleep mode. Putting the DAC into single DAC mode does not automatically assert this

signal, so for minimum power in single DAC mode, also program this register bit.

sleepa

When set, DACA is put into sleep mode. Note: If DACA channel is in sleep mode (sleepa = '1') the DACB channel

is also forced in to sleep mode.

isbiaslpfb_a

Turns on the low pass filter for the current source bias in the DACA when cleared. The low pass filter will set a

corner at ~472kHz when low and ~95 kHz when high.

isbiaslpfb_b

Turns on the low pass filter for the current source bias in the DACB when cleared. The low pass filter will set a

corner at ~472kHz when low and ~95 kHz when high.

PLL_sleep

When set, the PLL is put into sleep mode. Bypassing the PLL does not automatically but it into sleep mode.

PLL_ena

When set, the PLL is on and its output clock is being used as the DAC clock.

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