MAC7200 datasheet(309/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

231

bwc[1:0]

Bandwidth control. This two-bit field provides a mechanism to effectively throttle the amount of bus bandwidth

consumed by the DMA. In general, as the DMA processes the inner minor loop, it continuously generates

read/write, read/write, ... sequences until the minor count is exhausted. This field forces the DMA to stall after

the completion of each read/write access to control the bus request bandwidth seen by the platform’s

cross-bar arbitration switch. To minimize start-up latency, bandwidth control stalls are suppressed for the first

two AHB bus cycles and after the last write of each minor loop. The dynamic priority elevation setting elevates

the priority of the DMA as seen by the cross-bar arbitration switch for the executing channel. Dynamic priority

elevation is suppressed during the first two AHB bus cycles.

00 No dma_engine stalls

01 Dynamic priority elevation

10 dma_engine stalls for 4 cycles after each r/w

11 dma_engine stalls for 8 cycles after each r/w

major.linkch[5:

Link channel number. If TCD.major.e_link = 0) then

No channel-to-channel linking (or chaining) is performed after the outer "major" loop counter is exhausted.

else

After the "major" loop counter is exhausted, the dma_engine initiates a channel service request at the channel

defined by major.linkch[5:0] by setting that channel’s TCD.start bit. The value contained in major.linkch[5:0]

must not exceed the number of implemented channels.

done

Channel done. This flag indicates the DMA has completed the outer major loop. It is set by the dma_engine

as the citer count reaches zero; it is cleared by software, or the hardware when the channel is activated. This

bit must be cleared in order to write the major.e_link or e_sg bits.

active

Channel active. This flag signals the channel is currently in execution. It is set when channel service begins,

and is cleared by the dma_engine as the inner minor loop completes or if any error condition is detected.

major.e_link

Enable channel-to-channel linking on major loop complete. As the channel completes the outer major loop,

this flag enables the linking to another channel, defined by major.linkch[5:0]. The link target channel initiates

a channel service request via an internal mechanism that sets the TCD.start bit of the specified channel. To

support the dynamic linking coherency model, this field is forced to zero when written to while the TCD.done

bit is set.

0 The channel-to-channel linking is disabled.

1 The channel-to-channel linking is enabled.

e_sg

Enable scatter/gather processing. As the channel completes the outer major loop, this flag enables

scatter/gather processing in the current channel. If enabled, the dma_engine uses dlast_sga as a memory

pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control

descriptor into the local memory. To support the dynamic scatter/gather coherency model, this field is forced

to zero when written to while the TCD.done bit is set.

0 The current channel’s TCD is “normal” format.

1 The current channel’s TCD specifies a scatter gather format. The dlast_sga field provides a memory pointer

to the next TCD to be loaded into this channel after the outer major loop completes its execution.

d_req

Disable request. If this flag is set, the DMA hardware automatically clears the corresponding DMAERQ bit

when the current major iteration count reaches zero.

0 The channel’s DMAERQ bit is not affected.

1 The channel’s DMAERQ bit is cleared when the outer major loop is complete.

Table 12-28. TCDn Word 7 (TCDn.{biter, control/status}) Field Descriptions (Continued)

Field

Description

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