MAC7200 datasheet(312/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

234

Freescale Semiconductor

A general formula to compute the peak request rate (with overlapping requests) is:

PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ]

where:

PEAKreq - peak request rate

freq - platform frequency

entry - channel startup (4 cycles)

read_ws - wait states seen during the system bus read data phase

write_ws - wait states seen during the system bus write data phase

exit - channel shutdown (3 cycles)

For example: consider a platform with the following characteristics:

•

Platform SRAM can be accessed with one wait-state when viewed from the AMBA-AHB data

phase

•

All IPS reads require two wait-states, and IPS writes three wait-states, again viewed from the

system bus data phase

•

Platform operates at 150 MHz

For an SRAM to IPS transfer,

Eqn. 12-1

For an IPS to SRAM transfer,

Eqn. 12-2

Assuming an even distribution of the two transfer types, the average Peak Request Rate would be:

Eqn. 12-3

The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a

cold start (where no channel is executing, DMA is idle) are:

•

11 cycles for a software (TCD.start bit) request

•

12 cycles for a hardware (ipd_req signal) request

Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from

the internal registering of the ipd_req signals. For the peak request rate calculations above, the arbitration

and request registering is absorbed in or overlap the previous executing channel.

Note: When channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel

selection and startup. This allows the link channel or the scatter/gather channel to be eligible and

considered in the arbitration pool for next channel selection.

Table 12-30. DMA Peak Request Rate [MReq/sec]

Platform Speed

Request Rate

(zero wait state)

Request Rate

(with wait states)

66.6 MHz

7.4

5.8

PEAKreq

150 MHz

()

() 3

[]cycles

-------------------------------------------------------------------------------------

11.5 M req/sec

PEAKreq

150 MHz

()

() 3

[]cycles

-------------------------------------------------------------------------------------

12.5 M req/sec

PEAKreq

11.5 M req/sec

12.5 M req/sec

--------------------------------------------------------------------------------------

12.0 M req/sec

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