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MAC7200 Datasheet(PDF) 120 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 120 Page - Freescale Semiconductor, Inc

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Detailed Signal Descriptions
MAC7200 Microcontroller Family Reference Manual, Rev. 2
42
Freescale Semiconductor
either an open drain or push-pull pad. The pin can be configured as the input pin of the Serial Peripheral
Interface A (DSPI_A). It can be configured to wake the system out of low-power mode (DOZE) when an
external signal is applied using the interrupt functionality. When the Nexus Primary Port is selected and
active, this pin is used as the Nexus Message Start/End output.
4.3.15
PB[3] / SOUT_A / NEX1RDY — Port B I/O Pin, DSPI_A and Nexus
Primary
PB[3] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as the output pin of the Serial Peripheral
Interface A (DSPI_A). It can be configured to wake the system out of low-power mode (DOZE) when an
external signal is applied using the interrupt functionality. When the Nexus Primary Port is selected and
active, this pin is used as the Nexus Ready output.
4.3.16
PB[4] / SCK_A — Port B I/O Pin and DSPI_A
PB[4] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as serial clock pin SCK of the Serial
Peripheral Interface A (DSPI_A). It can be configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality.
4.3.17
PB[5] / PCS[0] / SS[0] — Port B I/O Pin and DSPI_A
PB[5] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[0] when in Master
mode, or as slave select pin SS when in Slave mode for the Serial Peripheral Interface A (DSPI_A). It can
be configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.18
PB[6:7] / PCS[1:2] — Port B I/O Pin and DSPI_A
PB[6] - PB[7] are configurable general purpose input or output pins. They can be configured to provide
either high or reduced output drives, to enable or disable either a pull-up or pull-down resistor on the pins
or to provide either open drain or push-pull pads. The pins can be configured as chip select pin PCS[1:2]
when in Master mode for the Serial Peripheral Interface A (DSPI_A). Each pin can be independently
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.19
PB[8] / PCS[5] / PCSS — Port B I/O Pin and DSPI_A
PB[8] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide



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