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6402 Datasheet(PDF) 178 Page - Intel Corporation |
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6402 Datasheet(HTML) 178 Page - Intel Corporation |
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178 / 250 page ![]() Registers 178 Intel® 6400/6402 Advanced Memory Buffer Datasheet 14.3.1.14 FBDLOCKTO: FBD Bit Lock Time Out Register This register contains the bit lock time out value. This value is used by the to figure out when it should stop waiting for lanes to bit lock and make forward progress. The register also contains the width that the host is going to be starting with on the NB side. This will be used to mask off lanes for initial bit lock decision 14.3.1.15 FBDHAC: FBD Hot Add Control This register contains control to aid in hot add functionality. 14.3.1.16 FBDLS: FBD Link Status This register reports AMB FBD link status. Device: NodeID Function: 1 Offset: 68h Bit Attr Default Description 15:2 RWST 0594h BLTOCNT: Bit Lock Time Out Counter default: 1428 frames 1:0 RWST 0h NBLINKCFG: Northbound Link Config 00 = 14 lane 01 = 13 lane 10 = 12 lane 11 = reserved Device: NodeID Function: 1 Offset: 6Ch Bit Attr Default Description 7:2 RV 0 Reserved 1 RO 0 NB_DATA_ALL_ONES_FLAG: • 1 = Receiving ones on sufficient NB lanes to support init • 0 = Not receiving calibrate handshake on NB Rx 0 RW 0 DRIVE_ONES_SB: • 1 = Enable SB Tx Outputs and drive one’s • 0 = Normal operation Device: NodeID Function: 1 Offset: 6Eh Bit Attr Default Description 7:3 RV 0h Reserved 2RO 0 NLQS: Northbound Lane Electrical Status ‘1’ = Northbound lanes are quiesced ‘0’ = Northbound lanes are active 1RO 0 SLQS: Southbound Lane Electrical Status ‘1’ = Southbound lanes are quiesced ‘0’ = Southbound lanes are active 0RO 0 LNKRDY: Link Ready ‘1’ = FBD link is ready to accept requests and deliver responses ‘0’ = FBD link is not ready |
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