ADS4225 datasheet(38/104 Pages) TI1

38 / 104 page

ADS4222, ADS4225, ADS4226

ADS4242, ADS4245, ADS4246

SBAS533C

– MARCH 2011 – REVISED JUNE 2011

www.ti.com

FREEZE OFFSET CORR

OFFSET CORR TIME CONSTANT

Bit 7

FREEZE OFFSET CORR: Freeze offset correction setting

This bit sets the freeze offset correction estimation.

0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)

1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen,

the last estimated value is used for offset correction of every clock cycle. See the Offset Correction

section.

Bit 6

Always write '0'

Bits[5:2]

OFFSET CORR TIME CONSTANT

The offset correction loop time constant in number of clock cycles. Refer to the Offset Correction

section.

Bits[1:0]

Always write '0'

LOW SPEED MODE CH B

Bits[7:1]

Always write '0'

Bit 0

LOW SPEED MODE CH B: Channel B low-speed mode enable

This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to '1'

before using this bit.

0 = Low-speed mode is disabled for channel B

1 = Low-speed mode is enabled for channel B

EN LOW SPEED MODE

Bits[7:5]

Always write '0'

Bit 4

EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits

(ADS42x5 and ADS42x6 only)

This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and LOW

SPEED MODE CH A register bits.

0 = Low-speed mode is disabled

1 = Low-speed mode is controlled by serial register bits

Bits[3:0]

Always write '0'

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Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246

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