ADS4225 datasheet(13/104 Pages) TI1

13 / 104 page

ADS4222, ADS4225, ADS4226

ADS4242, ADS4245, ADS4246

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SBAS533C

– MARCH 2011 – REVISED JUNE 2011

Pin Descriptions: LVDS Mode

PIN NUMBER

PIN NAME

# OF PINS

FUNCTION

DESCRIPTION

1, 48

DRVDD

Input

Output buffer supply

Serial interface RESET input.

When using the serial interface mode, the internal registers must be initialized

through a hardware RESET by applying a high pulse on this pin or by using the

RESET

Input

software reset option; refer to the Serial Interface Configuration section.

In parallel interface mode, the RESET pin must be permanently tied high. SCLK

and SEN are used as parallel control pins in this mode. This pin has an internal

150k

Ω pull-down resistor.

This pin functions as a serial interface clock input when RESET is low. It controls

SCLK

Input

the low-speed mode selection when RESET is tied high; see Table 5 for detailed

information. This pin has an internal 150k

Ω pull-down resistor.

SDATA

Input

Serial interface data input; this pin has an internal 150k

Ω pull-down resistor.

This pin functions as a serial interface enable input when RESET is low. It

controls the output interface and data format selection when RESET is tied high;

SEN

Input

see Table 6 for detailed information. This pin has an internal 150k

Ω pull-up

resistor to AVDD.

16, 22, 33, 34

AVDD

Input

Analog power supply

17, 18, 21, 24,

AGND

Input

Analog ground

27, 28, 31, 32

INP_B

Input

Differential analog positive input, channel B

INM_B

Input

Differential analog negative input, channel B

This pin outputs the common-mode voltage (0.95V) that can be used externally to

VCM

Output

bias the analog input pins

CLKP

Input

Differential clock positive input

CLKM

Input

Differential clock negative input

INP_A

Input

Differential analog positive input, channel A

INM_A

Input

Differential analog negative input, channel A

CTRL1

Input

Digital control input pins. Together, they control the various power-down modes.

CTRL2

Input

Digital control input pins. Together, they control the various power-down modes.

CTRL3

Input

Digital control input pins. Together, they control the various power-down modes.

49, PAD

DRGND

Input

Output buffer ground

CLKOUTM

Output

Differential output clock, complement

CLKOUTP

Output

Differential output clock, true

This pin functions as a serial interface register readout when the READOUT bit is

SDOUT

Output

enabled. When READOUT = 0, this pin is in high-impedance state.

Refer to

Figure 2 and

DA0P, DA0M

Output

Channel A differential output data pair, D0 and D1 multiplexed

Figure 3

Refer to

Figure 2 and

DA2P, DA2M

Output

Channel A differential output data D2 and D3 multiplexed

Figure 3

Refer to

Figure 2 and

DA4P, DA4M

Output

Channel A differential output data D4 and D5 multiplexed

Figure 3

Refer to

Figure 2 and

DA6P, DA6M

Output

Channel A differential output data D6 and D7 multiplexed

Figure 3

Refer to

Figure 2 and

DA8P, DA8M

Output

Channel A differential output data D8 and D9 multiplexed

Figure 3

Refer to

Figure 2 and

DA10P, DA10M

Output

Channel A differential output data D10 and D11 multiplexed

Figure 3

Refer to

Figure 2 and

DA12P, DA12M

Output

Channel A differential output data D12 and D13 multiplexed (ADS424x only)

Figure 3

Refer to

Figure 2 and

DB0P, DB0M

Output

Channel B differential output data pair, D0 and D1 multiplexed

Figure 3

Refer to

Figure 2 and

DB2P, DB2M

Output

Channel B differential output data D2 and D3 multiplexed

Figure 3

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