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ADS4225 Datasheet(PDF) 86 Page - Texas Instruments |
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ADS4225 Datasheet(HTML) 86 Page - Texas Instruments |
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86 / 104 page ![]() DB10_M DB10_P DB8_M DB8_P DB6_M DB6_P DB4_M DB4_P DB2_M DB2_P DB0_M DB0_P CLKOUTM CLKOUTP Pins 14-Bit ADCData, ChannelB Output Clock DataBits D10,D11 DataBits D8,D9 DataBits D6,D7 DataBits D4,D5 DataBits D2,D3 DataBits D0,D1 DB12_M DB12_P DataBits D12,D13 ADS4222, ADS4225, ADS4226 ADS4242, ADS4245, ADS4246 SBAS533C – MARCH 2011 – REVISED JUNE 2011 www.ti.com DDR LVDS Outputs In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 166. Figure 166. LVDS Interface 86 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246 |
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