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ADS4225 Datasheet(PDF) 89 Page - Texas Instruments |
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ADS4225 Datasheet(HTML) 89 Page - Texas Instruments |
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89 / 104 page  14-BitADCData, ChannelB DB0 DB1 DB2 DB11 DB12 DB13 SDOUT CLKOUT 14-BitADCData, ChannelA DA0 DA1 DA2 DA11 DA12 DA13 ADS4222, ADS4225, ADS4226 ADS4242, ADS4245, ADS4246 www.ti.com SBAS533C – MARCH 2011 – REVISED JUNE 2011 Parallel CMOS Interface In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle, as Figure 170 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. It is recommended to minimize the load capacitance of the data and clock output pins by using short traces to the receiver. Furthermore, match the output data and clock traces to minimize the skew between them. Figure 170. CMOS Outputs Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 89 Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246 |
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