ADS4225 datasheet(79/104 Pages) TI1

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ADS4222, ADS4225, ADS4226

ADS4242, ADS4245, ADS4246

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SBAS533C

– MARCH 2011 – REVISED JUNE 2011

Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This operation improves the

common-mode noise immunity and even-order harmonic rejection. A 5

Ω to 15Ω resistor in series with each input

pin is recommended to damp out ringing caused by package parasitics.

SFDR performance can be limited as a result of several reasons, including the effects of sampling glitches;

nonlinearity of the sampling circuit; and nonlinearity of the quantizer that follows the sampling circuit. Depending

on the input frequency, sample rate, and input amplitude, one of these factors plays a dominant part in limiting

performance. At very high input frequencies (greater than approximately 300MHz), SFDR is determined largely

by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually limits

performance.

Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a

low source impedance to absorb these glitches. Otherwise, glitches could limit performance, primarily at low

input frequencies (up to approximately 200MHz). It is also necessary to present low impedance (less than 50

Ω)

for the common-mode switching currents. This configuration can be achieved by using two resistors from each

input terminated to the common-mode voltage (VCM).

The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the

sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff

frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other hand, with a higher

cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches now must be

supplied by the external drive circuit. This tradeoff has limitations as a result of the presence of the package

bond-wire inductance.

In the ADS424x/422x, the R-C component values have been optimized while supporting high input bandwidth (up

to 550MHz). However, in applications with input frequencies up to 200MHz to 300MHz, the filtering of the glitches

can be improved further using an external R-C-R filter; see Figure 156 and Figure 157.

In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency

range and matched impedance to the source. Furthermore, the ADC input impedance must be considered.

Figure 154 and Figure 155 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins.

Figure 154. ADC Analog Input Resistance (RIN)

Figure 155. ADC Analog Input Capacitance (CIN)

Across Frequency

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ADS4225 Datasheet(PDF) 79 Page - Texas Instruments

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