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RM48L930 Datasheet(PDF) 115 Page - Texas Instruments |
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RM48L930 Datasheet(HTML) 115 Page - Texas Instruments |
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115 / 147 page ![]() V S1 On-State Leakage Off-State Leakages V S2 V S24 39*I AIL I AIL I AIL R ext R ext R ext P in S mux R mux P in S mux R mux P in S mux R mux S samp R samp C samp C ext I AIL I AIL I AIL I AIL C mux C ext C ext RM48L930 RM48L730 RM48L530 www.ti.com SPNS176 – SEPTEMBER 2011 Figure 5-1. MibADC Input Equivalent Circuit Table 5-7. MibADC Timing Specifications Parameter MIN NOM MAX Unit tc(ADCLK) (1) Cycle time, MibADC clock 0.033 µs td(SH) (2) Delay time, sample and hold 0.2 µs time 12-bit mode td©) Delay time, conversion time 0.4 µs td(SHC) (3) Delay time, total sample/hold 0.6 µs and conversion time 10-bit mode td©) Delay time, conversion time 0.33 µs td(SHC) (4) Delay time, total sample/hold 0.53 µs and conversion time (1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits 4:0. (2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD <GP>SAMP register for each conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as well as the ADC ’s internal impedance. (3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the prescale settings. (4) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the prescale settings. Copyright © 2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 115 Submit Documentation Feedback focus.ti.com: RM48L930 RM48L730 RM48L530 |
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