TLK105 datasheet(64/99 Pages) TI

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TLK105

TLK106

SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013

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8.11 LED Control Register (LEDCR)

This register provides the ability to directly manually control the Link LED output.

Table 8-26. LED Control Register (LEDCR), address 0x0018

BIT

NAME

DEFAULT

DESCRIPTION

15:11

RESERVED

<0000 0>, ro

RESERVED: Writes ignored, read as 0.

10:9

Blink Rate

<10>,RW

LED Blinking Rate (ON/OFF duration):

00 = 20Hz (50mSec)

01 = 10Hz (100mSec)

10 = 5Hz (200mSec)

11 = 2Hz (500mSec)

RESERVED

LED Link Polarity

1, RW,

LED Link Polarity Setting:

Pin_Strap

1 = Active High polarity setting

0 = Active Low polarity setting

Link LED polarity defined by strapping value of this pin. This register allows

override of this strapping value.

RESERVED

Drive Link LED

0,RW

Drive LED Link to the forced On/Off setting defined in bit 1:

1 = Drive value of On/Off bit onto LED_LINK output pin

0 = Normal operation

RESERVED

Link LED On/Off Setting

0,RW

Value to force on Link LED output

RESERVED

8.12 PHY Control Register (PHYCR)

This register provides the ability to control and set general functionality inside the PHY.

Table 8-27. PHY Control Register (PHYCR), address 0x0019

BIT

NAME

DEFAULT

DESCRIPTION

Auto MDI/X

1, RW,

Auto-MDIX Enable:

Enable

Pin_Strap

1 = Enable Auto-negotiation Auto-MDIX capability

0 = Disable Auto- negotiation Auto-MDIX capability

Force MDI/X

0, RW

Force MDIX:

1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair)

0 = Normal operation. (Transmit on TPTD pair, Receive on TPRD pair)

Pause RX

0, RO

Pause Receive Negotiated Status: Indicates that pause receive should be enabled in the MAC.

Status

Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings.

This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause

Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.

Pause TX

0,RO

Pause Transmit Negotiated Status:

Status

Indicates that pause transmit should be enabled in the MAC. Based on bits [11:10] in ANAR register

and bits [11:10] in ANLPAR register settings.

This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause

Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.

MI Link

0, RO

MII Link Status:

Status

1 = 100BT Full-duplex Link is active and it was established using Auto-Negotiation

0 = No active link of 100BT Full-duplex, established using Auto-Negotiation

10:8

RESERVED

<000>, RO

RESERVED: Writes ignored, read as 0.

Bypass LED

0, RW

Bypass LED Stretching:

Stretching

1 = Bypass LED stretching

0 = Normal LED operation

Set this bit to 1 to bypass the LED stretching; the LED reflects the internal value.

RESERVED

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