TLK105 datasheet(3/99 Pages) TI

3 / 99 page

TLK105

TLK106

www.ti.com

SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Introduction

.............................................. 1

6.1

Hardware Reset

.................................... 33

1.1

Features

............................................. 1

6.2

Software Reset

..................................... 33

1.2

Applications

.......................................... 1

6.3

Power Down/Interrupt

.............................. 33

1.3

Device Overview

..................................... 1

6.4

Power Save Modes

................................. 34

Pin Descriptions

......................................... 4

Design Guidelines

..................................... 35

2.1

Pin Layout

........................................... 4

7.1

TPI Network Circuit

................................. 35

2.2

Serial Management Interface (SMI)

................. 5

7.2

Clock In (XI) Requirements

......................... 35

2.3

MAC Data Interface

.................................. 5

7.3

Thermal Vias Recommendation

.................... 37

2.4

10Mbs and 100Mbs PMD Interface

.................. 6

......................................... 38

2.5

Clock Interface

....................................... 6

8.1

.................................. 43

2.6

LED Interface

........................................ 6

8.2

Extended Register Addressing

..................... 55

2.7

Reset and Power Down

............................. 6

8.3

PHY Status Register (PHYSTS)

................... 57

2.8

Power and Bias Connections

........................ 7

8.4

PHY Specific Control Register (PHYSCR)

......... 58

Hardware Configuration

............................... 7

8.5

MII Interrupt Status Register 1 (MISR1)

............ 59

3.1

Bootstrap Configuration

.............................. 7

8.6

MII Interrupt Status Register 2 (MISR2)

............ 60

3.2

Power Supply Configuration

......................... 8

8.7

False Carrier Sense Counter Register (FCSCR)

... 61

3.3

IO Pins Hi-Z State During Reset

..................... 9

8.8

Receiver Error Counter Register (RECR)

.......... 61

3.4

Auto-Negotiation

.................................... 10

8.9

BIST Control Register (BISCR)

.................... 61

3.5

Auto-MDIX

.......................................... 10

8.10

RMII Control and Status Register (RCSR)

......... 62

3.6

MII Isolate Mode

.................................... 11

8.11

LED Control Register (LEDCR)

.................... 64

3.7

PHY Address

....................................... 11

8.12

PHY Control Register (PHYCR)

.................... 64

3.8

LED Interface

....................................... 12

8.13

10Base-T Status/Control Register (10BTSCR)

.... 65

3.9

Loopback Functionality

............................. 13

8.14

BIST Control and Status Register 1 (BICSR1)

..... 65

3.10

BIST

................................................ 15

8.15

BIST Control and Status Register2 (BICSR2)

..... 66

3.11

Cable Diagnostics

.................................. 15

8.16

Cable Diagnostic Control Register (CDCR)

........ 67

Interfaces

................................................ 17

8.17

PHY Reset Control Register (PHYRCR)

........... 67

4.1

Media Independent Interface (MII)

................. 17

8.18

TX_CLK Phase Shift Register (TXCPSR)

.......... 67

4.2

Reduced Media Independent Interface (RMII)

..... 18

8.19

Voltage Regulator Control Register (VRCR)

....... 68

8.20

Cable Diagnostic Configuration/Result Registers

4.3

Serial Management Interface

....................... 20

(TLK106)

............................................ 68

Architecture

............................................. 24

Electrical Specifications

............................. 74

5.1

100Base-TX Transmit Path

......................... 24

9.1

ABSOLUTE MAXIMUM RATINGS

................. 74

5.2

100Base-TX Receive Path

......................... 27

9.2

RECOMMENDED OPERATING CONDITIONS

.... 74

5.3

10Base-T Receive Path

............................ 29

9.3

THERMAL CHARACTERISTICS

................... 74

5.4

Auto Negotiation

.................................... 30

9.4

DC CHARACTERISTICS

5.5

Link Down Functionality

............................ 31

9.5

POWER SUPPLY CHARACTERISTICS

Reset and Power Down Operation

................. 33

9.6

AC Specifications

Contents

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