TLK105 datasheet(19/99 Pages) TI

19 / 99 page

PHY

MAC

TXD[1:0]

TX_EN

TXD[1:0]

RX_ER

RXD[1:0]

RX_DV (optional)

RX_DV

RX_ER

RXD[1:0]

CRS/RX_DV

50MHz

Clock Source

RX_CLK (optional)

RX_CLK

TLK105

TLK106

www.ti.com

SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013

Figure 4-2. TLK10x RMII/MAC Connection

RMII function includes a programmable elastic buffer to adjust for the frequency differences between the

reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal

propagation delay based on expected maximum packet size and clock accuracy.

Table 4-1 indicates how to program the buffer FIFO based on the expected max packet size and clock

accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same

accuracy.

Table 4-1. Recommended RMII Packet Sizes

Recommended packet size at

Start Threshold RBR[1:0]

Latency Tolerance

±50ppm

±100ppm

1(4-bits)

2 bits

2400 bytes

1200 bytes

2(8-bits)

6 bits

7200 bytes

3600 bytes

3(12-bits)

10 bits

12000 bytes

6000 bytes

0(16-bits)

14 bits

16800 bytes

8400 bytes

Interfaces

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TLK105 Datasheet(PDF) 19 Page - Texas Instruments

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