TLK105 datasheet(7/99 Pages) TI

7 / 99 page

TLK105

TLK106

www.ti.com

SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013

2.8

Power and Bias Connections

TYPE

DESCRIPTION

NAME

NO.

RBIAS

Bias Resistor Connection: Use a 4.87k

Ω 1% resistor connected from RBIAS to GND.

PFBOUT

Power Feedback Output: Place 10µf and 0.1

μF capacitors (ceramic preferred) close to PFBOUT.

In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 13 and pin 24). See Figure 3-1

for proper placement.

In multiple supply operation, this pin is not used.

Power Feedback Input: These pins are fed with power from PFBOUT (pin 15) in single supply

PFBIN1

operation.

In multiple supply operation, connect a 1.55V external power supply to these pins. Connect a small

PFBIN2

capacitor of 0.1µF close to each pin. To power down the internal linear regulator, write to register

0x00d0.

VDD33_IO

I/O 3.3V Supply

AVDD33

Analog 3.3V power supply

Ground

Ground Pad

GND

Pad

Hardware Configuration

This section includes information on the various configuration options available with the TLK10x. The

configuration options described below include:

•

Bootstrap Configuration

•

PHY Address

•

Power Supply Configuration

•

LED Interface

•

IO Pins Hi-Z State During Reset

•

Loopback Functionality

•

Auto-Negotiation

•

BIST

•

Auto-MDIX

•

Cable Diagnostics (TLK106 only)

•

MII Isolate mode

3.1

Bootstrap Configuration

Bootstrap configuration is a convenient way to configure the TLK10x into specific modes of operation.

Some of the functional pins are used as configuration inputs. The logic states of these pins are sampled

during reset and are used to configure the device into specific modes of operation. The table below

describes bootstrap configuration.

A 2.2k

Ω resistor is used for pull-down or pull-up to change the default configuration. If the default option is

desired, then there is no need for external pull-up or pull down resistors. Because these pins may have

alternate functions after reset is deasserted, they must not be connected directly to VCC or GND.

TYPE

NAME

NO.

DESCRIPTION

PHYAD0 (COL)

PHY Address [4:0]: The TLK10x provides five PHY address pins, the states of which are

PHYAD1 (RXD_0)

latched into an internal register at system hardware reset. The TLK10x supports PHY

S, O, PD /

PHYAD2 (RXD_1)

Address values 0 (<00000>) through 31 (<11111>). PHYAD[4:1] pins have weak internal

PHYAD3 (RXD_2)

pull-down resistors, and PHYAD[0] has weak internal pull-up resistor, setting the default

PHYAD4 (RXD_3)

PHYAD if no external resistors are connected.

AN_0: FD-HD config. FD = pull up.

AN_0 (LED_LINK)

S, O, PU

The default wake-up is auto negotiation enable 100BT.

This option selects the operation mode of the LED LINK pin. Default is Mode 1. All modes

LED_CFG (CRS)

S, O, PU

are also configurable via register access. See PHY Control Register (PHYCR), Address

0x0019.

Hardware Configuration

Submit Documentation Feedback

Product Folder Links: TLK105 TLK106

TLK105 Datasheet(PDF) 7 Page - Texas Instruments

TLK105 Datasheet(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

Datasheet Download

Link URL