TLK105 datasheet(18/99 Pages) TI

18 / 99 page

TLK105

TLK106

SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013

www.ti.com

4.2

Reduced Media Independent Interface (RMII)

TLK10x incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII

specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost

alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification

provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence

of an MII.

The RMII specification has the following characteristics:

•

Supports 10Mbs and 100Mbs data rates

•

Single clock reference sourced from the MAC to PHY (or from an external source)

•

Provides independent 2 bit wide (di-bit) transmit and receive data paths

•

Uses CMOS signal levels, the same levels as the MII interface

In this mode, data transfers two bits at a time using the 50MHz RMII reference clock for both transmit and

receive. RMII mode uses the following pins:

Signal

XI (RMII reference clock is 50MHz)

TXD_0

TXD_1

TX_EN

CRS_DV

RX_ER

RXD_0

RXD_1

Data on TXD [1:0] are latched at the PHY with reference to the reference-clock edges on the XI pin. Data

on RXD [1:0] are latched at the MAC with reference to the same reference clock edges on the XI pin. The

RMII operates at the same speed (50MHz) in both 10B-T and 100B-TX. In 10B-T the data is 10 times

slower than the reference clock, so transmit data is sampled every 10 clocks. Likewise, receive data is

generated on every 10th clock so that an attached MAC device can sample the data every 10 clocks.

In addition, RMII mode supplies an RX_DV signal which allows a simpler method of recovering receive

data without the need to separate RX_DV from the CRS_DV indication. RMII mode requires a 50MHz

oscillator to be connected to the device XI pin.

The TLK10x supports a special mode called “RMII receive clock” mode. This mode, which is not part of

the RMII specification, allows synchronization of the MAC-PHY RX interface. In this mode, the PHY

generates a recovered 50MHz clock through the RX_CLK pin and synchronizes the RXD[1:0], CRS_DV,

RX_DV and RX_ER signals to this clock. Setting register 0x000A bit [0] is required to activate this mode.

Figure 4-2 describes the RMII signals connectivity between the TLK10x and any MAC device.

Interfaces

Submit Documentation Feedback

Product Folder Links: TLK105 TLK106

TLK105 Datasheet(PDF) 18 Page - Texas Instruments

TLK105 Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

Datasheet Download

Link URL