TLK105 datasheet(79/99 Pages) TI

79 / 99 page

TX_CLK

TX_EN

TXD

PMD Output Pair

(J/K)

IDLE

DATA

T0343-01

RX_CLK

Valid Data

RXD[3:0]

RX_DV

RX_ER

T0342-01

TLK105

TLK106

www.ti.com

SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013

9.6.5

100Mb/s MII Receive Timing

Table 9-5. 100Mb/s MII Receive Timing

PARAMETER(1)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RX_CLK High Time

100Mbs Normal mode

RX_CLK Low Time

RX_CLK to RXD[3:0], RX_DV, RX_ER Delay

100Mbs Normal mode

(1)

RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high

and low times will not be violated.

Figure 9-5. 100Mb/s MII Receive Timing

9.6.6

100Base-TX Transmit Packet Latency Timing

Table 9-6. 100Base-TX Transmit Packet Latency Timing

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TX_CLK to PMD Output Pair Latency

100Mbs Normal mode(1)

4.8

bits(2)

(1)

For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of

TX_EN to the first bit of the 'J' code group as output from the PMD Output Pair. 1 bit time = 10ns in 100Mbs mode.

(2)

1 bit time is equal 10 nS in 100 Mb/s mode.

Figure 9-6. 100Base-TX Transmit Packet Latency Timing

Electrical Specifications

Submit Documentation Feedback

Product Folder Links: TLK105 TLK106

TLK105 Datasheet(PDF) 79 Page - Texas Instruments

TLK105 Datasheet(HTML) 79 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

Datasheet Download

Link URL