DAC3151 datasheet(35/57 Pages) TI

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D15

D14

D13

D12

D11

D10

Instruction Cycle

Data Transfer Cycle

tS (SDENB)

tS(SDIO) tH(SDIO)

SCLK

SDENB

SCLK

SDIO

SDENB

SCLK

SDIO

DAC3151

DAC3161

DAC3171

www.ti.com

SLAS959A – AUGUST 2013 – REVISED AUGUST 2013

SERIAL INTERFACE DESCRIPTION

The serial port of the DAC3151/DAC3161/DAC3171 is a flexible serial interface which communicates with

industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers

used to define the operating modes of DAC3151/DAC3161/DAC3171. It is compatible with most synchronous

transfer formats and can be configured as a 3 or 4 pin interface by sif4_ena in register XYZ. In both

configurations, SCLK is the serial interface input clock and SDENB is serial interface enable. For 3 pin

configuration, SDIO is a bidirectional pin for both data in and data out. For 4 pin configuration, SDIO is data in

only and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is output from the

device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte

is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit

address to be accessed. Table 5 indicates the function of each bit in the instruction cycle and is followed by a

detailed description of each bit. The data transfer cycle consists of two bytes.

Table 5. Instruction Byte of the Serial interface

MSB

LSB

Bit

Description

R/W

Identifies the following data transfer cycle as a read or write operation. A high indicates a read

operation from DAC3151/DAC3161/DAC3171 and a low indicates a write operation to

DAC3151/DAC3161/DAC3171.

[A6 : A0]

Identifies the address of the register to be accessed during the read or write operation.

Figure 70 shows the serial interface timing diagram for a DAC3151/DAC3161/DAC3171 write operation. SCLK is

the serial interface clock input to DAC3151/DAC3161/DAC3171. Serial data enable SDENB is an active low input

to DAC3151/DAC3161/DAC3171. SDIO is serial data in. Input data to DAC3151/DAC3161/DAC3171 is clocked

on the rising edges of SCLK.

Figure 70. Serial Interface Write Timing Diagram

Figure 71 shows the serial interface timing diagram for a DAC3151/DAC3161/DAC3171 read operation. SCLK is

the serial interface clock input to DAC3151/DAC3161/DAC3171. Serial data enable SDENB is an active low input

to DAC3151/DAC3161/DAC3171. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO

is data out from the DAC3151/DAC3161/DAC3171 during the data transfer cycle, while SDO is in a high-

impedance

state.

configuration,

both

SDIO

and

SDO

are

data

out

from

the

DAC3151/DAC3161/DAC3171 during the data transfer cycle. At the end of the data transfer, SDIO and SDO will

output low on the final falling edge of SCLK until the rising edge of SDENB when they will 3-state.

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