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DAC3151 Datasheet(PDF) 19 Page - Texas Instruments |
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DAC3151 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 57 page ![]() DAC3151 DAC3161 DAC3171 www.ti.com SLAS959A – AUGUST 2013 – REVISED AUGUST 2013 ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued) Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50% clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise noted). DAC3151 DAC3161 DAC3171 TEST PARAMETER UNIT CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX LVDS INPUT TIMING config3 Setting datadly clkdly 0 0 -20 -20 -20 0 1 -120 -120 -120 D[x..0] valid to DATACLK 0 2 -220 -220 -220 rising or falling edge for single bus single clock 0 3 -310 -310 -310 mode ; 0 4 -390 -390 -390 _ DA/DB[x…0] valid to 0 5 -480 -480 -480 DB_CLK rising or falling edge ts(DATA) Setup time for dual bus single clock 0 6 -560 -560 -560 ps mode; 0 7 -630 -630 -630 _ DA[x..0] valid to DA_CLK 1 0 70 70 70 rising or falling edge, and 2 0 150 150 150 DB[x…0] valid for DB_CLK rising or falling edge for dual 3 0 230 230 230 bus dual clock mode 4 0 330 330 330 5 0 430 430 430 6 0 530 530 530 7 0 620 620 620 congfig3 Setting datadly clkdly 0 0 310 310 310 0 1 390 390 390 D[x..0] valid to DATACLK 0 2 480 480 480 rising or falling edge for 0 3 560 560 560 single bus single clock mode; _ 0 4 650 650 650 DA/DB[x…0] valid to 0 5 740 740 740 DB_CLK rising or falling edge for dual bus single clock th(DATA) Hold time 0 6 850 850 850 ps mode; _ 0 7 930 930 930 DA[x..0] valid to DA_CLK 1 0 200 200 200 rising or falling edge, and DB[x…0] valid for DB_CLK 2 0 100 100 100 rising or falling edge for dual 3 0 20 20 20 bus dual clock mode. 4 0 -60 -60 -60 5 0 -140 -140 -140 6 0 -220 -220 -220 7 0 -290 -290 -290 Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: DAC3151 DAC3161 DAC3171 |
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