DAC3151 datasheet(40/57 Pages) TI

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DAC3151

DAC3161

DAC3171

SLAS959A – AUGUST 2013 – REVISED AUGUST 2013

www.ti.com

Addr

Bit

Name

Function

Default Value

Name

(Hex)

config3

0x03

15:13

datadlya

Controls the delay of the A data inputs through the LVDS receivers. 000

0= no additional delay and each LSB adds a nominal 80ps.

12:10

clkdlya

Controls the delay of the A data clock input through the LVDS

000

receivers. 0= no additional delay and each LSB adds a nominal

80ps.

9:7

reserved

reserved.

000

6:4

reserved

000

extref_ ena

Enable external reference for the DAC when set.

2:1

reserved

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config4

0x04

15:14

reserved

WRITE TO

13:0

iotest_ results

The values of these bits tell which bit in the input word failed during the

0x0000

CLEAR/

io-test pattern comparison.

No RESET

value

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config5

0x05

alarm_from_ zerochka

When this bit is asserted the FIFOA write pointer has an all zeros

WRITE TO

pattern in it. Since this pointer is a shift register, all zeros will cause

CLEAR

the input point to be stuck until the next sync. The result could be a

repeated 8T pattern at the output if the mixer is off and no syncs

occur. Check for this error will tell the user that another sync is

necessary to restart the FIFO write pointer.

reserved

reserved.

13:11

alarms_from_ fifoa

These bits report the FIFO A pointer status.

000

000: All fine

001: Pointers are 2 away

01X: Pointers are 1 away

1XX: FIFO Pointer collision

10:8

reserved

alarm_dacclk_ gone

Bit gets asserted when the DACCLK has been stopped long for

enough cycles to be caught. The number of cycles varies with

interpolation.

alarm_dataclk_ gone

Bit gets asserted when the DATACLK has been stopped long for

enough cycles to be caught. The number of cycles varies with

interpolation.

clock_gone

This bit gets set when either alarm_dacclk_gone or

alarm_dataclk_gone are asserted. It controls the output of the

CDRV_SER block. When high, the CDRV_SER block will output

“0x8000” for each output connected to a DAC. The bit must be

written to ‘0’ for CDRV_SER outputs to resume normal operation.

alarm_from_ iotesta

This is asserted when the input data pattern does not match the

pattern in the iotest_pattern registers.

reserved

reserved.

reserved

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