DAC3151 datasheet(11/57 Pages) TI

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DAC3151

DAC3161

DAC3171

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SLAS959A – AUGUST 2013 – REVISED AUGUST 2013

PIN ASSIGNMENT TABLE – DAC3171 7-BIT INTERFACE MODE (continued)

I/O

DESCRIPTION

NAME

NO.

DATA INTERFACE

DA[6:0]P/N

9/10-

LVDS positive input data bits for channel A. Each positive/negative LVDS pair has an internal 100

19/20

termination resistor. Data format relative to DA_CLKP/N clock is Double Data Rate (DDR) with two

data transfers per DA_CLKP/N clock cycle.

22/23

The data format is 7 MSBs (rising edge)/7 LSBs falling edge.

In the default mode (reverse bus not enabled):

D6P/N is most significant data bit (MSB)

D0P/N is most significant data bit (LSB)

DA_CLKP/N

6/7

DDR differential input data clock for channel A. Edge to center nominal timing.

OUTPUT/CLOCK

DACCLKP/N

1/2

LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.

IOUTAP/N

61/60

A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a

full scale current source and the most positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data

input results in a 0 mA current source and the least positive voltage on the IOUTA1 pin. The IOUTA2

pin is the complement of IOUTA1.

REFERENCE

EXTIO

I/O

Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling

capacitor to GND when used as reference output.

BIASJ

Full-scale output current bias. For 20 mA full-scale output current, connect a 960

Ω resistor to GND.

POWER SUPPLY

IOVDD

Supply voltage for CMOS IO’s. 1.8V – 3.3V.

CLKVDD18

1.8V clock supply

DIGVDD18

21, 28

1.8V digital supply. Also supplies LVDS receivers.

VDDA18

50, 64

Analog 1.8V supply

VDDA33

55, 56,

Analog 3.3V supply

VFUSE

Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to

DVDD pins for normal operation.

4,5,

Not used. Pin 4 can be left open or tied to DIGVDD18, and other pins can be left open or tied to

24/25,

GROUND in actual application use. It is recommended to turn off pin 24/25, 26/27, 29/30-39/40

26/27

(register lvdsdataclk_ena, lvdsdata_ena) to save power.

29/30-

39/40,

51, 52,

53, 53,

62, 63

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