Electronic Components Datasheet Search
  English  ▼

X  

DAC3151 Datasheet(PDF) 18 Page - Texas Instruments

Click here to check the latest version.
Part # DAC3151
Description  Single 14-/12-/10-Bit 500 MSPS Digital-to-Analog Converters
PDF  57 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC3151 Datasheet(HTML) 18 Page - Texas Instruments

Back Button DAC3151 Datasheet HTML 14Page - Texas Instruments DAC3151 Datasheet HTML 15Page - Texas Instruments DAC3151 Datasheet HTML 16Page - Texas Instruments DAC3151 Datasheet HTML 17Page - Texas Instruments DAC3151 Datasheet HTML 18Page - Texas Instruments DAC3151 Datasheet HTML 19Page - Texas Instruments DAC3151 Datasheet HTML 20Page - Texas Instruments DAC3151 Datasheet HTML 21Page - Texas Instruments DAC3151 Datasheet HTML 22Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 57 page
background image
DAC3151
DAC3161
DAC3171
SLAS959A – AUGUST 2013 – REVISED AUGUST 2013
www.ti.com
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50%
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
DAC3151
DAC3161
DAC3171
TEST
PARAMETER
UNIT
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
CMOS DIGITAL INPUTS (RESETB, SDENB, SCLK, SDIO, TXENABLE)
0.6×
0.6×
0.6×
VIH
High-level input voltage
V
IOVDD
IOVDD
IOVDD
0.25×
0.25×
0.25×
IOVDD = 3.3 V, 2.5 V or
VIL
Low-level input voltage
V
IOVDD
IOVDD
IOVDD
1.8 V
IIH
High-level input current
-40
40
–40
40
μA
IIL
Low-level input current
-40
40
–40
40
μA
DIGITAL OUTPUTS – CMOS INTERFACE (SDOUT, SDIO)
IOVDD = 3.3 V, 2.5 V,
0.85×
0.85×
0.85×
VOH
High-level output voltage
V
1.8 V
IOVDD
IOVDD
IOVDD
0.125×
0.125×
0.125×
VOL
Low-level output voltage
V
IOVDD
IOVDD
IOVDD
SERIAL PORT TIMING
ts(SENDB)
Setup time, SDENB to rising edge of SCLK
20
20
20
ns
ts(SDIO)
Setup time, SDIO to rising edge of SCLK
10
10
10
ns
th(SDIO)
Hold time, SDIO from rising edge of SCLK
5
5
5
ns
t(SCLK)
Period of SCLK
100
100
100
ns
t(SCLKH)
High time of SCLK
40
40
40
ns
t(SCLKL)
Low time of SCLK
40
40
40
ns
td(DATA)
Data output delay after falling edge of SCLK
10
10
10
ns
TRESET
Minimum RESTB pulsewidth
25
25
25
ns
LVDS INTERFACE (D[x..0]P/N, DA[x..0]P/N , DB[x..0]P/N , DA_CLKP/N, DB_CLKP/N, DATACLKP/N, SYNCP/N, ALIGNP/N)
VA,B+
Logic high differential input voltage threshold
175
175
175
mV
VA,B–
Logic low differential input voltage threshold
–175
–175
–175
mV
VCOM
Input Common Mode Range
1.0
1.2
2.0
1.0
1.2
2.0
1.0
1.2
2.0
V
ZT
Internal termination
85
110
135
85
110
135
85
110
135
Ω
CL
LVDS input capacitance
2
2
2
pF
18
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DAC3151 DAC3161 DAC3171



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com