LPC4370 datasheet(56/150 Pages) NXP

56 / 150 page

LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

56 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

[6]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDD(IO) present;

if VDD(IO) not present, do not exceed 3.3 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital

section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP

[7]

5 V tolerant transparent analog pad.

[8]

For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS

= 0.2 V when it is no longer driven.

[9]

Transparent analog pad. Not 5 V tolerant.

[10] Pad provides USB functions (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V). It is designed in accordance

with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).

[11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to

provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

[12] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.

[13] To minimize interference on the 12-bit ADC signal lines, do not configure the digital signal as output when using the 12-bit ADC. See

Table 42.

LPC4370 Datasheet(PDF) 56 Page - NXP Semiconductors