LPC4370 datasheet(66/150 Pages) NXP

66 / 150 page

LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

66 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

7.15 One-Time Programmable (OTP) memory

The OTP provides 64-bit + 256 bit of memory for general purpose use.

7.16 General Purpose I/O (GPIO)

The LPC4370 provide 8 GPIO ports with up to 31 GPIO pins each.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

All GPIO pins default to inputs with pull-up resistors enabled on reset.

7.16.1 Features

• Accelerated GPIO functions:

– GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or

level-sensitive GPIO interrupt request (GPIO interrupts).

• Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO

group0 and group1 interrupts).

7.17 Configurable digital peripherals

7.17.1 State Configurable Timer (SCT) subsystem

The SCT allows a wide variety of timing, counting, output modulation, and input capture

operations. The inputs and outputs of the SCT are shared with the capture and match

inputs/outputs of the 32-bit general purpose counter/timers.

The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the

two-counter case, in addition to the counter value the following operational elements are

independent for each half:

• State variable

• Limit, halt, stop, and start conditions

• Values of Match/Capture registers, plus reload or capture control values

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