LPC4370 datasheet(57/150 Pages) NXP

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LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

57 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses allow for concurrent code and data

accesses from different slave ports.

The LPC4370 use a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and

other bus masters to peripherals in a flexible manner that optimizes performance by

allowing peripherals that are on different slaves ports of the matrix to be accessed

simultaneously by different bus masters.

An ARM Cortex-M0 coprocessor is included in the LPC4370, capable of off-loading the

main ARM Cortex-M4 application processor. Most peripheral interrupts are connected to

both processors. The processors communicate with each other via an interprocessor

communication protocol.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture

with separate local instruction and data buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A

hardware floating-point processor is integrated in the core. The processor includes a

NVIC with up to 53 interrupts.

7.3 ARM Cortex-M0 processors

The ARM Cortex-M0 processors are general purpose, 32-bit microprocessors, which offer

high performance and very low power consumption. The ARM Cortex-M0 processor uses

a 3-stage pipeline von Neumann architecture and a small but powerful instruction set

providing high-end processing hardware. The processors each incorporate an NVIC with

32 interrupts.

7.3.1 ARM Cortex-M0 coprocessor

The M0 coprocessor resides on the same AHB multi-layer matrix as the main Cortex-M0

core. The coprocessor can be used to off-load multiple tasks from the main Cortex-M4

processor.

7.3.2 ARM Cortex-M0 subsytem

The Cortex-M0 subsystem can be used to manage the SGPIO and SPI peripherals on the

M0 subsystem multilayer matrix but any other peripheral as well. The M0 subsystem is

separated by a bridge from the main AHB matrix. The M0 subsystem AHB matrix has two

SRAM blocks which allows to run the Cortex-M0 subsytem at full speed independently

from the main matrix.

One application of using the subsystem is to reduce power, for example when the main

matrix runs at a very low speed and the M0 subsystem monitors activity and increases the

main matrix speed when needed.

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