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LPC4370 Datasheet(PDF) 93 Page - NXP Semiconductors

Part # LPC4370
Description  32-bit ARM Cortex-M4 2 x M0 MCU 282 kB SRAM Ethernet two HS USBs 80 Msps 12-bit ADC configurable peripherals
PDF  150 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC4370 Datasheet(HTML) 93 Page - NXP Semiconductors

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LPC4370
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 21 October 2013
93 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply voltages.
[2]
Dynamic characteristics for peripherals are provided for VDD(REG)(3V)  2.7 V.
[3]
Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure
the same ramp-up time for both supply voltages.
[4]
VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V; Tamb =25 C.
[5]
PLL1 disabled; IRC running; CCLK = 12 MHz.
[6]
VBAT = 3.6 V.
[7]
VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 180 MHz.
[8]
On pin VBAT; Tamb =25 C.
[9]
VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V. Input leakage increases when VDD(IO) is floating or grounded. It is recommended to keep
VDD(REG)(3V3) and VDD(IO) powered in deep power-down mode.
[10] Vps corresponds to the output of the power switch (see Figure 7) which is determined by the greater of VBAT and VDD(Reg)(3V3).
[11] VDDA(3V3) = 3.3 V; Tamb =25 C.
[12] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[13] To VSS.
[14] The values specified are simulated and absolute values.
[15] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level.
[16] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO).
[17] The parameter value specified is a simulated value excluding bond capacitance.
[18] For USB operation 3.0 V
 V
DD((IO)  3.6 V. Guaranteed by design.
[19] VDD(IO) present.
[20] Includes external resistors of 33
 1 % on D+ and D.
VOH
HIGH-level output
voltage (driven) for
low-/full-speed
RL of 15 k to GND
2.8
-
3.5
V
Ctrans
transceiver capacitance pin to GND
-
-
20
pF
ZDRV
driver output
impedance for driver
which is not high-speed
capable
with 33
 series resistor;
steady state drive
[20] 36
-
44.1
Table 10.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit



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