LPC4370 datasheet(61/150 Pages) NXP

61 / 150 page

LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

61 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

7.9 Global Input Multiplexer Array (GIMA)

The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers,

event router, or the ADCs.

7.9.1 Features

• Single selection of a source.

• Signal inversion.

• Can capture a pulse if the input event source is faster than the target clock.

• Synchronization of input event and target clock.

• Single-cycle pulse generation for target.

7.10 System Tick timer (SysTick)

The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

7.11 On-chip static RAM

The LPC4370 support 200 kB local SRAM and an additional 64 kB AHB SRAM with

separate bus master access for higher throughput and individual power control for low

power operation. See Section 7.23.9.1 “Memory retention in Power-down modes”.

7.12 In-System Programming (ISP)

In-System programming (ISP) is programming or reprogramming the on-chip SRAM

memory, using the boot loader software and the USART0 serial port. This can be done

when the part resides in the end-user board. ISP allows to load data into on-chip SRAM

and execute code from on-chip SRAM.

7.13 Boot ROM

The internal ROM memory is used to store the boot code of the LPC4370. After a reset,

the ARM processor will start its code execution from this memory.

The boot ROM memory includes the following features:

• ROM memory size is 64 kB.

• Supports booting from UART interfaces and external static memory such as NOR

flash, SPI flash, quad SPI flash.

• Includes APIs for OTP programming.

• Includes a flexible USB device stack that supports Human Interface Device (HID),

Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.

Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If

the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is

determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.

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