LPC4370 datasheet(77/150 Pages) NXP

77 / 150 page

LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

77 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

7.20.3.1

Features

• Tracks encoder position.

• Increments/decrements depending on direction.

• Programmable for 2 or 4 position counting.

• Velocity capture using built-in timer.

• Velocity compare function with “less than” interrupt.

• Uses 32-bit registers for position and velocity.

• Three position compare registers with interrupts.

• Index counter for revolution counting.

• Index compare register with interrupts.

• Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

• Digital filter with programmable delays for encoder input signals.

• Can accept decoded signal inputs (clk and direction).

7.20.4 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 32-bit counter which is compared to

a selectable value, generating an interrupt when a match occurs. Any bits of the

timer/compare can be masked such that they do not contribute to the match detection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.20.4.1

Features

• 32-bit counter. Counter can be free-running or be reset by a generated interrupt.

• 32-bit compare value.

• 32-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

7.20.5 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.20.5.1

Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

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