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LPC4370 Datasheet(PDF) 62 Page - NXP Semiconductors

Part # LPC4370
Description  32-bit ARM Cortex-M4 2 x M0 MCU 282 kB SRAM Ethernet two HS USBs 80 Msps 12-bit ADC configurable peripherals
PDF  150 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC4370 Datasheet(HTML) 62 Page - NXP Semiconductors

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LPC4370
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 21 October 2013
62 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
[1]
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
[1]
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Table 4.
Boot mode when OTP BOOT_SRC bits are programmed
Boot mode BOOT_SRC
bit 3
BOOT_SRC
bit 2
BOOT_SRC
bit 1
BOOT_SRC
bit 0
Description
Pin state
0
0
0
0
Boot source is defined by the reset state of P1_1,
P1_2, P2_8 pins, and P2_9. See Table 5.
USART0
0
0
0
1
Boot from device connected to USART0 using pins
P2_0 and P2_1.
SPIFI
0
0
1
0
Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
EMC 8-bit
0
0
1
1
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit
0
1
0
0
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit
0
1
0
1
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0
011
0Boot from USB0.
USB1
011
1Boot from USB1.
SPI (SSP)
1
0
0
0
Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].
USART3
1
0
0
1
Boot from device connected to USART3 using pins
P2_3 and P2_4.
Table 5.
Boot mode when OPT BOOT_SRC bits are zero
Boot mode
Pins
Description
P2_9
P2_8
P1_2
P1_1
USART0
LOW
LOW
LOW
LOW
Boot from device connected to USART0 using pins
P2_0 and P2_1.
SPIFI
LOW
LOW
LOW
HIGH
Boot from Quad SPI flash connected to the SPIFI
interface on P3_3 to P3_8[1].
EMC 8-bit
LOW
LOW
HIGH
LOW
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit
LOW
LOW
HIGH
HIGH
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit
LOW
HIGH
LOW
LOW
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0
LOW
HIGH
LOW
HIGH
Boot from USB0
USB1
LOW
HIGH
HIGH
LOW
Boot from USB1.
SPI (SSP)
LOW
HIGH
HIGH
HIGH
Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].
USART3
HIGH
LOW
LOW
LOW
Boot from device connected to USART3 using pins
P2_3 and P2_4.



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