AD9775 datasheet(5/56 Pages) AD

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AD9775

Rev. E | Page 5 of 56

SPECIFICATIONS

DC SPECIFICATIONS

TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

RESOLUTION

Bits

DC Accuracy1

Integral Nonlinearity

−5

±1.5

LSB

Differential Nonlinearity

−3

±1.0

LSB

ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)

Offset Error

−0.02

±0.01

+0.02

% of FSR

Gain Error (with Internal Reference)

−1.0

+1.0

% of FSR

Gain Matching

−1.0

±0.1

+1.0

% of FSR

Full-Scale Output Current2

Output Compliance Range

−1.0

+1.25

Output Resistance

200

kΩ

Output Capacitance

Gain, Offset Cal DACs, Monotonicity Guaranteed

REFERENCE OUTPUT

Reference Voltage

1.14

1.20

1.26

Reference Output Current3

100

REFERENCE INPUT

Input Compliance Range

0.1

1.25

Reference Input Resistance

kΩ

Small Signal Bandwidth

0.5

MHz

TEMPERATURE COEFFICIENTS

Offset Drift

ppm of FSR/°C

Gain Drift (with Internal Reference)

ppm of FSR/°C

Reference Voltage Drift

±50

ppm/°C

POWER SUPPLY

AVDD

Voltage Range

3.1

3.3

3.5

Analog Supply Current (IAVDD)4

72.5

IAVDD in SLEEP Mode

23.3

CLKVDD

Voltage Range

3.1

3.3

3.5

Clock Supply Current (ICLKVDD)4

8.5

10.0

CLKVDD (PLL ON)

Clock Supply Current (ICLKVDD)

23.5

DVDD

Voltage Range

3.1

3.3

3.5

Digital Supply Current (IDVDD)4

Nominal Power Dissipation

380

410

PDIS5

1.75

PDIS IN PWDN

6.0

Power Supply Rejection Ratio—AVDD

±0.4

% of FSR/V

OPERATING RANGE

−40

+85

°C

1 Measured at IOUTA driving a virtual ground.

2 Nominal full-scale current, IOUTFS, is 32 × the IREF current.

3 Use an external amplifier to drive any external load.

4 100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

5 400 MSPS fDAC = 50 MSPS, fS/2 modulation, PLL enabled.

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