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AD9775

Rev. E | Page 28 of 56

fDATA (MHz)

100

150

200

Figure 51 ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled

SLEEP/POWER-DOWN MODES

(Control Register 0x00, Bit 3 and Bit 4)

The AD9775 provides two methods for programmable

reduction in power savings. The sleep mode, when activated,

turns off the DAC output currents but the rest of the chip

remains functioning. When coming out of sleep mode, the

AD9775 immediately returns to full operation. Power-down

mode, on the other hand, turns off all analog and digital

circuitry in the AD9775 except for the SPI port. When

returning from power-down mode, enough clock cycles must

be allowed to flush the digital filters of random data acquired

during the power-down cycle.

TWO-PORT DATA INPUT MODE

The digital data input ports can be configured as two independ-

ent ports or as a single (one-port mode) port. In two-port mode,

data at the two input ports is latched into the AD9775 on every

rising edge of the data rate clock (DATACLK). Also, in two-port

mode, the AD9775 can be programmed to generate an externally

available DATACLK for the purpose of data synchronization.

This data rate clock can be programmed to be available at either

Pin 8 (DATACLK/PLL_LOCK) or Pin 53 (SPI_SDO). Because

Pin 8 can also function as a PLL lock indicator when the PLL is

enabled, there are several options for configuring Pin 8 and

Pin 53. The following sections describe the options.

PLL Off (Register 4, Bit 7 = 0)

PLL On (Register 4, Bit 7 = 1)

of Pin 8.

of Pin 53.

In one-port mode, P2B14 and P2B15 from Input Data Port 2

are redefined as IQSEL and ONEPORTCLK, respectively. The

input data in one-port mode is steered to one of the two inter-

nal data channels based on the logic level of IQSEL. A clock

signal, ONEPORTCLK, is generated by the AD9775 in this

mode for the purpose of data synchronization. ONEPORTCLK

runs at the input interleaved data rate, which is 2× the data rate

at the internal input to either channel.

Figure 101 through Figure 104 illustrate the test configurations

showing the various clocks that are required and generated by

the AD9775 with the PLL enabled/disabled and in the one-

port/two-port modes. Jumper positions needed to operate the

AD9775 evaluation board in these modes are given as well.

PLL ENABLED, TWO-PORT MODE

(Control Register 0x02, Bit 6 to Bit 0 and

Control Register 0x04, Bit 7 to Bit 1)

With the phase-locked loop (PLL) enabled and the AD9775 in

two-port mode, the speed of CLKIN is inherently that of the

input data rate. In two-port mode, Pin 8 (DATACLK/PLL_

LOCK) can be programmed (Control Register 0x01, Bit 0) to

function as either a lock indicator for the internal PLL or as a

clock running at the input data rate. When Pin 8 is used as a

clock output (DATACLK), its frequency is equal to that of

CLKIN. Data at the input ports is latched into the AD9775 on

the rising edge of the CLKIN. Figure 52 shows the delay, tOD,

inherent between the rising edge of CLKIN and the rising edge

of DATACLK, as well as the setup and hold requirements for

the data at Ports 1 and 2. The setup and hold times given in

Figure 52 are the input data transitions with respect to CLKIN.

Note that in two-port mode (PLL enabled or disabled), the data

rate at the interpolation filter inputs is the same as the input

data rate at Port 1 and Port 2.

The DAC output sample rate in two-port mode is equal to the

clock input rate multiplied by the interpolation rate. If zero

stuffing is used, another factor of 2 must be included to

calculate the DAC sample rate.

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