AD1803 datasheet(11/32 Pages) AD

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AD1803

THEORY OF OPERATION

SERIAL INTERFACE MODE SELECTION

By default the AD1803 uses Slot 5 to send and receive sample

When power is first applied to the AD1803, RESET must be

data, but this can be changed to Slot 10 or Slot 11. See the

asserted (RESET pin driven low), and kept asserted until the

SPCHN bit, SPGBP bit, SPDSS bit, SPISO bit, SPDL1 bit, and

SPDL0 bit in Register 0x5E for additional AC '97 mode con-

power has stabilized. While RESET is asserted, the AD1803’s

figuration enhancements.

serial interface mode is chosen by the state of Pin 12

(G[3]/WAKE) and Pin 13 (G[2]).

AC '97 INTERFACE MODES

Table 7.

Primary Mode

Pin 12

Pin 13

Mode Chosen

High

Low

High

Low

High

Low

AC '97 Mode—Primary Device (ID: 00)

AC '97 Mode—Secondary Device (ID: 01)

AC '97 Mode—Secondary Device (ID: 10)

DSP Mode

Entered if G[3] pin and G[2] pin are high when the RESET pin

is deasserted for the first time:

•

AD1803 is the timing master: drives BIT_CLK at

12.288 MHz.

Note that Pin 12 and Pin 13 have weak pull-up devices internal

•

AD1803 accepts the 48 kHz SYNC timing signal.

to the AD1803 that are enabled by default. Therefore, if these

pins are floated, AC '97 primary mode is chosen. When RESET

•

AD1803 requires a crystal or clock on XTALI (see the

is deasserted (RESET pin driven high) for the first time after

XTAL1 bit and XTAL0 bit in Register 0x5C for frequency).

power is applied, the states of Pin 12 and Pin 13 are latched,

Secondary Mode

locking in serial interface mode. Subsequent changes of the

logic level presented on Pin 12 and Pin 13 have no effect on

Entered if the G[3] pin is high and G[2] pin is low when the

serial port mode until power is removed from the AD1803.

RESET pin is deasserted for the first time or if the G[3] pin is

After this first deassertion of RESET, Pin 12 and Pin 13 take

low and the G[2] pin is high when the RESET pin is deasserted

on new roles and serve as general-purpose I/O control pins.

for the first time:

The AD1803 does not need an active clock source for proper

•

AD1803 is the timing slave: accepts BIT_CLK at

operation during this mode selection.

12.288 MHz.

SERIAL INTERFACE BEHAVIOR AND PROTOCOL

WHEN IN AC '97 MODE

•

AD1803 accepts the 48 kHz SYNC timing signal.

The AD1803 serial interface is compatible with the AC '97

•

AD1803 does not require a crystal or clock on XTALI

Rev 2.1 specification as either a primary or a secondary

(see the XTAL1 bit and XTAL0 bit in Register 0x5C for

modem/handset codec device. Consult this specification

frequency), unless wake from an event during RESET is

for complete behavioral details.

desired. XTALI okay here?

SLOT #

SYNC

CMD

ADDR

CMD

DATA

TAG

PCM

LINE1

DAC

PCM

CENTER

PCM

L SURR

PCM

R SURR

PCM

LFE

LINE2

DAC

HSET

DAC

I/O

CTRL

SDATA_OUT

(OUTPUT FROM CONTROLLER/DSP – INPUT TO AD1803)

(INPUT TO CONTROLLER/DSP – OUTPUT FROM AD1803)

Figure 10. AC '97 Interface Timing

STATUS

ADDR

STATUS

DATA

TAG

MIC

ADC

LINE2

ADC

RSRVD

RSRVD RSRVD

HSET

I/O

STATUS

PCM

LINE1

ADC

SDATA_IN

Rev. A | Page 11 of 32

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