AD1803 datasheet(12/32 Pages) AD

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AD1803

SERIAL INTERFACE BEHAVIOR AND PROTOCOL

WHEN IN DSP MODE

In DSP mode, the AD1803 requires a clock on XTALI to func

tion properly. This clock can be created by placing a crystal

between Pin XTALI and Pin XTALO with appropriate trim

capacitors. Alternatively, a clock can be driven directly onto

the XTALI pin from an external source, in which case XTALO

must be floated. When the AD1803 serial interface is configured in

DSP mode, the clock presented on the XTALI pin is assumed to

be 24.576 MHz. However, a 12.288 MHz or 32.768 MHz clock

could be used instead, providing

• A register write informs the AD1803 of the true clock

frequency before the codec is enabled.

• It is acceptable to have the serial port bit clock and frame

sync run at rates different from the start-up nominal until

the AD1803 is informed of the true XTALI clock frequency.

Within 1 ms after RESET is deasserted and the AD1803 receives

a clock on XTALI, the AD1803 begins driving a 4.096 MHz bit

clock onto the BIT_CLK pin (assuming a 24.576 MHz XTALI

clock). Approximately 100 μs later, the AD1803 begins driving

an 8 kHz frame sync onto the SYNC pin (again assuming a

24.576 MHz XTALI clock). If the AD1803 receives an XTALI

clock that is higher/lower than the expected 24.576 MHz default,

these frequencies are scaled up/down (lineally) until the AD1803

is informed of the actual XTALI clock frequency by a write to

the XTAL1 and XTAL0 bits in Register 0x5C. See the XTAL1

and XTAL0 bits for further details including allowed alternate

XTALI frequencies.

Each serial interface frame consists of a single 16-bit word sent

into the AD1803 on the SDATA_OUT pin, and a single 16-bit

word sent out of the AD1803 on the SDATA_IN pin. These words

are simultaneously transferred during the first 16 clocks of the

BIT_CLK pin after the start of a frame. The start of a frame is

marked by one BIT_CLK long high pulse of the SYNC pin one

BIT_CLK period before the first bit in the frame. Data is trans

mitted MSB first. Logic levels on all pins (SYNC, SDATA_IN,

and SDATA_OUT) are updated on BIT_CLK rising edges, and

should be sampled on BIT_CLK falling edges.

By default, all frames are designated as data frames for delivery

of two’s complement DAC and ADC samples to and from the

AD1803 codec. To deliver control information into the part,

the LSB of the word into the AD1803 is stolen, from what

might otherwise have been DAC data, to serve as a control

frame request bit.

While the AD1803 provides 16-bit ADC sample output, only

15-bit DAC sample input is possible because of this. If the LSB

of the word into the AD1803 is set to 0, no control frame is

requested and the next frame is another data frame. If the

LSB of the word into the AD1803 is set to 1, a control frame

is requested and the next frame is a control frame.

When a control frame is requested, an extra frame is inserted

between data frames avoiding an interruption of codec sample

data flow. The 16-bit control word into the AD1803 consists of

(from MSB to LSB):

•

A register read/write request bit (0 to request a write, 1 to

request a read).

•

The 6 MSBs of a 7-bit register address (where the LSB is

removed to save space since it is always a 0).

•

A byte select bit (0 to select the lower byte of the 16-bit

control register addressed, 1 to select the upper byte of

the 16-bit control register addressed).

•

Eight bits of data that are written into the addressed register

if a write is requested. Otherwise, these last eight bits are

ignored.

While it seems peculiar to have a 7-bit register address with

the LSB dropped when sent to the AD1803, it should be noted

that AD1803 register addresses are defined by the AC '97 specifica

tion, whether configured in an AC '97 mode or in DSP mode.

While the AC ’97 Rev 2.1 specification reserves odd addresses

for future feature expansion, there was no room in the DSP mode

control word for this unused bit. The 16-bit control word out

of the AD1803 consists of, from MSB to LSB, eight unused bits

that are always set to 0, followed by eight bits of data that reflect

the contents of the register addressed within the current frame, if

a read was requested. Otherwise, they are all set to 0.

When serial interface frames first commence after RESET is

deasserted, there are 512 bits per frame (8 kHz frame rate/

4.096 MHz bit clock rate) where only the first 16 bits per frame

are typically utilized. Bits out of the AD1803 after the first 16

are typically set to 0, and bits into the AD1803 after the first 16

are typically ignored. However, when a control frame is requested

via the control frame request bit in a data frame, the control

frame is inserted between data frames and placed 256 bits after

the start of the data frame that requested the control frame. This

control frame is marked by an additional 1-bit long clock pulse,

high of the SYNC pin. Note that the spacing between data frames

is never affected by the insertion of a control frame.

Rev. A | Page 12 of 32

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