AD1803 datasheet(13/32 Pages) AD

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AD1803

The frame rate at startup is 8 kHz and there are exactly 512 bits

from the start of one data frame to the next; this changes as soon

as the codec is enabled (the codec is powered down by default

after power is first applied to the AD1803). Whenever the

codec is enabled, the frame rate is switched from 8 kHz to the

programmed codec sample rate, and whenever the codec is

powered down again, the frame rate switches back to 8 kHz. With

the bit clock always fixed at 4.096 MHz, this gives rise to a first

cause of variation in the number of bits between starts of data

frames. A second cause of a varying number of bits between

starts of data frames is the presence of a subtle jitter in the asser

tion of frame sync when the codec is enabled. On average, there

is an exact match between the programmed sample rate and the

frame rate; the frame sync itself varies up to 4% of a sample

period from the ideal assertion point in time.

FRAME TYPES:

SYNC

When the serial interface is in DSP mode, it is possible to access

only the upper or lower 8-bit byte of a 16-bit control register at

a time. While this is sufficient for manipulating many of the

AD1803 features, some features require more than eight control

bits and span multiple 8-bit bytes and/or multiple 16-bit words.

To allow all bits of a feature to take effect simultaneously, writes

to certain control bytes of certain registers are actually held in

holding latches until a particular control byte of the feature is

written. Note that a read of a control register always returns the

contents of a holding latch (if present for that register), which

does not necessarily reflect the control setting currently being

used by the AD1803. The only feature that incorporates this com

plication is the codec sample rate, which writes to the lower byte

of Register 0x40 and does not take effect until the upper byte of

OUTPUT FROM AD1803 (EIGHT ZEROS, FOLLOWED BY EIGHT BITS OF REGISTER READ DATA ADDRESSED

BY THIS FRAME)

FREQUENCY: 8kHz WHEN CODEC DISABLED, AND EQUAL TO SAMPLE RATE WHEN CODEC ENABLED

FREQUENCY: 4.096MHz

INPUT TO AD1803 (15 TRANSMIT SAMPLE DATA BITS, PLUS CONTROL FRAME REQUEST BIT)

OUTPUT FROM AD1803 (16 CAPTURE SAMPLE DATA BITS)

INPUT TO AD1803 (READ/WRITE, ADDRESS, AND BYTE SELECT, FOLLOWED BY EIGHT BITS OF

C15 C14 C13 C12 C11 C10

T15 T14 T13 T12 T11 T10

BIT_CLK

DATA FRAME (16 BITS):

SDATA_OUT

SDATA_IN

CONTROL FRAME (16 BITS):

SDATA_OUT

SDATA_IN

Figure 11. Frame Types

FRAME INSERTED IF REQUESTED BY CR BIT

FRAME ORDERING:

SYNC

DATA FRAME

CONTROL FRAME

DATA FRAME

T15:1, CR

RW, A6:1,

B, W7:0

IGNORED

T15:1, CR

SDATA_OUT

R7:0

C15:0

SDATA_IN

PERIOD EQUALS 1/8kHz WHEN CODEC IS DISABLED AND

PROGRAMMED SAMPLE PERIOD WHEN CODEC IS ENABLED

Figure 12. Frame Ordering

Rev. A | Page 13 of 32

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