AD1803

Rev. A | Page 21 of 32

GPIO PIN WAKE-UP MASK

Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x52

0

0

0

0

0

0

0

0

GW7

GW6

GW5

GW4

GW3

GW2

GW1

GW0

0x0000

This register is forced to its default only when power is first applied to the AD1803.

Bit Name

Description

GW7 to

GW0

GPIO Wake-Up Mask Control. A GPIO pin triggers an interrupt providing that it is enabled to cause interrupts by the corresponding

numbered bit in this register, and it has its associated sticky status bit set. For the associated sticky status bit to be set, the GPIO

input must first be enabled to be sticky by the GS bit in Register 0x50, and then the logic level selected by a GP bit in Register 0x4E

must be received on the associated GPIO pin. When an interrupt is triggered, Pin 12 is driven high providing Pin 12 is enabled to

serve as an interrupt output (see GPWAK bit in Register 0x5E). If the AD1803’s serial interface is configured in an AC '97 mode,

interrupts are also reflected on Bit 0 of Slot 12 of each frame, even if Pin 12 is not enabled to respond to an interrupt. Also in AC '97

mode, if RESET is asserted when an interrupt is triggered, the SDATA_IN pin is driven from low (default during RESET) to high to

wake an AC '97 controller. Refer to the AC '97 specification for complete details. Activated GPIO pins can trigger interrupts. The

source of the interrupt can be determined by reading Register 0x54.

0 = GPIO pin disabled from causing interrupts (default).

1 = GPIO pin enabled to cause interrupts (providing corresponding GS bit in Register 0x50 = 1).

GPIO PIN STATUS REGISTER

Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x54

0

0

0

0

0

0

0

0

GI7

GI6

GI5

GI4

GI3

GI2

GI1

GI0

0x00FF

This register is forced to its default only when power is first applied to the AD1803.

Bit Name

Description

GI7 to GI0

GPIO Status. Each bit corresponds with a GPIO pin of the same number. When a bit is read, it reflects either the current logic level

received on a GPIO pin or the state of the sticky status bit that is set if a selected logic level has been received on a GPIO pin since

the last time the sticky status bit was cleared (see Register 0x4E, Register 0x50, and Register 0x52). When a bit is written with a 0, the

associated sticky status bit is cleared. Note that it is not necessary to write a 1 to a bit after writing a 0 since it is the act of writing a 0

to a bit itself that clears the sticky status bit. When a bit is written with a 1, the associated sticky status bit is unaffected. If the

AD1803’s serial interface is configured in DSP mode (see Register 0x3C), writes to this register also control the logic level driven out

on the GPIO pins provided that a GPIO pin is configured as an output (see Register 0x4C) and is serving as a GPIO pin (see

Register 0x5E). If the AD1803’s serial interface is configured in an AC '97 mode, GPIO output states are determined by the bits in ac

link slot 12 rather than writes to this register (see Bit SPGBP in Register 0x5E and the AC '97 specification for further details).

MISCELLANEOUS MODEM AFE STATUS AND CONTROL REGISTER

Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x56

0

0

0

MLNK

0

0

0

0

0

0

0

0

0

LIB2

LIB1

LIB0

0x0000

This register is forced to its default only when power is first applied to the AD1803.

Bit Name

Description

MLNK

AC Link Disable. This bit has no effect on the behavior of the AD1803 unless it is configured as an AC '97 primary device (see

Register 0x3C). When this is the case, writing a 1 to this bit puts the AC '97 link interface into a sleep mode by causing the AD1803

to drive the BIT_CLK pin low within one BIT_CLK period after the completion of Slot 2 (the slot in which writes to control registers

occur). While in this sleep mode, an AC '97 controller can wake the AD1803 interface either by pulsing the SYNC pin, or by

asserting and then deasserting the RESET pin. Refer to the AC '97 specification for complete details. Note that the interface is put

to sleep, regardless of interface mode, if the RESET pin is asserted.

LIB2 to LIB0

Loopback Modes.

000 = No loopback. Normal signal pathways engaged (default).

001 = Analog loopback. Analog ADC output to analog DAC input (at analog interface to digital codec).

010 = Local loopback. DAC output to ADC input (at analog pins).

011 = Digital loopback. Digital DAC output to digital ADC input (at digital interface to analog codec).

1xx = No loopback. Normal signal pathways engaged.