AD1803 datasheet(31/32 Pages) AD

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AD1803

Rev. A | Page 31 of 32

Bit[0]—GSTA (GPIO status). This bit exists solely for AC '97

compatibility. Its purpose is to provide a handshake for power-

up/power-down status changes initiated by writes to Bit GPDN.

Because the AD1803 responds to a write of Bit GPDN prior to

it being possible to read this bit in a following serial interface

frame, there is no reason to poll this status bit.

Step 8:

Write to Register 0x5C (Configuration 1 Register).

The purpose of this write is to change the register bank selection

in preparation for Step 9. The value written to Register 0x5C at

this time should be identical to the value from Step 1, except

with Bits[14:13] (BNK1, BNK0) set to 10.

Step 9:

Write to Register 0x62 Bank 2 (Monitor Output Control

Writes to this register have no purpose unless a pin has been

assigned to serve as a monitor output (see Step 3 in the Typical

Initialization Sequence Immediately After First section). This

channel, select the mix of ADC and DAC channels delivered to

the monitor output, and select the order of the Σ-Δ monitor

output bit stream.

TYPICAL CODEC POWER-DOWN SEQUENCE

There are two ways to power down the codec. The first way is to

simply assert RESET (drive RESET pin low). This clears register

0x3E to its initial power-up default, powering down the ADC,

DAC, and voltage reference of the AD1803. A second method is

outlined below.

Step 1:

Write to Register 0x3E (Extended Status and Control

Bit[11]—DPDN (DAC power-down). This bit must be set to 1

to power down the DAC channel of the AD18103.

Bit[10]—APDN (ADC power-down). This bit must be set to 1

to power down the ADC channel of the AD18103.

Bit[9]—VPDN (voltage reference power-down). This bit can be

set to 1 to power down the voltage reference of the AD1803 and

save approximately 200 μA, but it can be desirable to leave the

voltage reference powered up. Leaving it powered up saves about

48 ms from a future codec power-up sequence, and avoids

potential clicks caused by the DAC output tracking the voltage

reference as it falls to 0 volts when powered down, and rises to

~1.25 V when powered back up.

Bit[8]—GPDN (GPIO power-down). This bit can be set to any

value because it has no effect on AD1803 operation when in

DSP mode.

Bit[1]—VSTA (voltage reference status). This bit can be polled

to determine the status of the part’s voltage reference. When

read as a 0, the voltage reference is either powered down or in

the process of powering up. When read as a 1, the voltage

reference is either powered up or in the process of powering

down. Within 0.8 ms after VPDN is set to 0, this bit transitions

from 1 to 0, indicating that the voltage reference is completely

powered down. If a clock is driven onto the XTALI pin, and it is

desired to stop this clock for additional system power savings,

this clock must not be stopped until after this bit falls to a 0.

TYPICAL CHIP POWER-DOWN SEQUENCE

Once the codec is powered down to the level desired, no add-

itional power can be saved unless the AD1803 receives a RESET,

ignoring power potentially saved by stopping the clock on

the CLK_OUT pin or disabling GPIO pin drivers, which have

resistive loads. When a RESET is received by the AD1803, the

serial interface automatically powers down, leaving the internal

clock generation and distribution circuitry of the part as the final

significant power consumer to be addressed. If Bit R34PM in

circuitry is powered down as well when RESET is asserted, with

the consequence that wake-up on ring and ability to source a clock

on the CLK_OUT pin during RESET is lost. This leaves silicon

leakage current, typically less than 100 μA, plus inadvertent serial

interface loading as the final power drains. Inadvertent serial

interface loading can be due to either the AD1803 receiving

intermediate or switching logic levels on its BIT_CLK, SYNC,

or SDATA_OUT input pins, or the presence of resistive loads to

a potential other than DGND (AD1803 digital ground) on the

SDATA_IN or BIT_CLK output pins. This inadvertent serial

interface loading can be eliminated if Bit SPISO (Serial Port

Isolate) in Register 0x5E is set to 1 before the part receives a

RESETwith the consequence that output BIT_CLK is driven

low weakly (<200 μA drive current) whenever RESET is asserted.

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