AD1803

Rev. A | Page 17 of 32

CONTROL REGISTER DETAILS

EXTENDED MODEM ID REGISTER

Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x3C

ID1

ID0

0

0

0

0

0

0

0

0

0

0

0

0

0

LIN1

0xX00X

A write to this register has no effect on the states of bits within this register, but does trigger Register 0x3E and Bank 2 Register 0x60 to be

cleared to their default states, powering down the AD1803’s codec resources.

Bit Name

Description

ID1, ID0

Interface Identification. These bits can be read to determine the AD1803’s serial interface mode of operation. Serial interface mode

is chosen by the states of Pin 13 and Pin 12 when RESET is deasserted (RESET pin driven from low to high) for the first time after

power is applied to the AD1803.

00 = AC link primary (mode chosen if Pin 12 is high and Pin 13 is high on first deassertion of RESET).

01 = AC link secondary (mode chosen if Pin 12 is high and Pin 13 is low on first deassertion of RESET).

10 = AC link secondary (mode chosen if Pin 12 is low and Pin 13 is high on first deassertion of RESET).

11 = DSP link (mode chosen if Pin 12 is low and Pin 13 is low on first deassertion of RESET).

LIN1

Modem Line 1 Supported. For AC '97 compatibility, this bit returns a 1 when read to indicate that the AD1803 supports AC '97

modem line 1 features.

EXTENDED STATUS AND CONTROL REGISTER

Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x3E

Res1

DPDN

APDN

VPDN

GPDN

0

0

0

0

DSTA

ASTA

VSTA

GSTA

0xFF00

This register is forced to its default when power is first applied to the AD1803, the RESET pin is driven low, or Register 0x3C is written with

any value.

Bit Name

Description

DPDN

DAC Power-Down. When this bit is set to 1 (default), all DAC resources within the AD1803 are powered down, and all DAC data sent

over the serial interface is ignored. When this bit is set to 0, the digital DAC resources are powered up. The analog DAC resources are

powered up only if the voltage reference of the AD1803 is powered up (Bit VPDN in this register is set to 0), and the analog codec of

the AD1803 is selected as the partner to the digital codec of the part (Bit ACSEL in Register 0x5C is set to 0).

0 = Enable digital DAC resources; conditionally enable analog DAC resources.

1 = Power-down all AD1803 DAC resources (default).

APDN

ADC Power-Down. When this bit is set to 1 (default), all ADC resources within the AD1803 are powered down, and all ADC data-words

sent out of the AD1803 over the serial interface are midscale (zero) and tagged invalid if the serial interface is configured in an AC '97

mode. When this bit is set to 0, the digital ADC resources within the AD1803 are powered up. The analog ADC resources within the

AD1803 are powered up only if both the voltage of the AD1803 reference is powered up (Bit VPDN in this register is set to 0), and the

analog codec of the AD1803 is selected as the partner to the digital codec of the part (Bit ACSEL in Register 0x5C is set to 0). Each

time the analog codec is powered up, an ADC dc offset calibration is automatically initiated. This calibration requires approximately

104 sample periods (defined by Register 0x40). It cannot be started until after the voltage reference is powered up (set Bit VPDN in

this register to 0), which requires about 48 ms. Bit VSTA in this register can be polled first to determine if the voltage reference is

powered up and then Bit ADCAL in Register 0x5C can be polled to determine if calibration is complete. During calibration, codec

sample rate, ADC source, and ADC gain level must not be changed.

0 = Enable AD1803 digital ADC resources; conditionally enable AD1803 analog ADC resources.

1 = Power-down all AD1803 ADC resources (default).

VPDN

Voltage Reference Power-Down. Writes to this bit initiate codec voltage reference power-up and power-down sequences. Bit VSTA in

this register can be polled to monitor current voltage reference status. Until the voltage reference is powered up, the analog ADC and

DAC channels of the AD1803 ignore the settings of Bit APDN and Bit DPDN and the part remains powered down.

0 = Enable voltage reference.

1 = Power-down voltage reference (default).