AD1803

Rev. A | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Conditions............................................................................. 3

Typical Supply Current ................................................................ 5

Timing Specifications .................................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Environmental Conditions.......................................................... 8

Package Characteristics ............................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Theory of Operation ...................................................................... 11

Serial Interface Mode Selection................................................ 11

Serial Interface Behavior and Protocol When in AC '97

Mode ............................................................................................ 11

AC '97 Interface Modes ............................................................. 11

Serial Interface Behavior and Protocol When in DSP Mode 12

Register Banks............................................................................. 14

Register Access Restrictions...................................................... 14

General-Purpose I/O Pin Operation ....................................... 14

Control Register Map..................................................................... 15

Control Register Details................................................................. 17

Extended Modem ID Register .................................................. 17

Extended Status and Control Register..................................... 17

Line DAC/ADC Sample Rate Control Register ..................... 18

DAC/ADC Level Control Register........................................... 19

GPIO Pin Configuration Register............................................ 20

GPIO Pin Polarity/Type Register ............................................. 20

GPIO Sticky Pin Register .......................................................... 20

GPIO Pin Wake-Up Mask......................................................... 21

GPIO Pin Status Register .......................................................... 21

Miscellaneous Modem AFE Status and Control Register..... 21

Configuration 1 Register ........................................................... 22

Configuration 2 Register ........................................................... 23

Bank 1—GPIO Initial States Register ...................................... 24

Bank 1—Clock Pad Control Register ...................................... 24

Bank 2 - Monitor Output Control Register ............................ 25

Version ID Register .................................................................... 25

Vendor ID1 Register .................................................................. 26

Vendor ID2 Register .................................................................. 26

Applications..................................................................................... 27

Application Circuits ................................................................... 27

Typical Initialization Sequence Immediately After First

RESET .......................................................................................... 29

Typical Codec Power-Up Sequence ......................................... 30

Typical Codec Power-Down Sequence.................................... 31

Typical Chip Power-Down Sequence ...................................... 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

12/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Figure 18...................................................................... 28

Changes to Ordering Guide .......................................................... 32

8/01—Revision 0: Initial Version